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LM5118. Problem with re-layout of Eval circuit.

John Cameron1
Prodigy 40 points
Other Parts Discussed in Thread: LM5118

Hi,

I have an application requirement that almost exactly matches the LM5118 Eval board;

Vin = 6 to 67V

Vout = 12V

Iout(max) = 3A.

I added some additional input circuit and designed a 2-layer version of the Eval board. This maybe my problem and I would appreciate some input!

Note: Component references are for my schematic, not the eval schematic.

For testing I have bypassed the additional input circuit; Vin is directly connected to C1-5 with a short length of 1mm2 wire. Vin is supplied from a bench PSU capable of 10A up to 15V and 5A up to 35V, the current limit is set to 10A.

I have the following problems.

  1. With no load, I have only 2V output at any input voltage up to 35V. This was improved by increasing the soft start capacitor from 100nF to 1uF. (Hint from another forum thread.)
  2. With the change in C17, Vout is 12V if there is no load. Vin immediately falls if a small load (470R) is connected to the output.
  3. Vout will only rise to 12V if Vin > 12V. Vin can then be reduced and Vout will remain at 12V (no load).
The schematic, PCB layout and BOM are in the attached PDF. 
It seems likely that my layout is the cause of my problems but I would appreciate some help in determining the reasons and eliminating other possible causes before I re-spin the PCB.
Thanks,
John.

 

  • 0
    TI__Guru 58761 points

    Hi

    Please check your SS and UVLO pin voltages when the output is not regulated. This is to check whether LM5118 is in hiccup mode or not

    LM5118 datasheet page 18;
    To further protect the external switches during prolonged overload conditions, an internal counter detects consecutive cycles of current limiting. If the counter
    detects 256 consecutive current limited PWM cycles, the LM5118 enters a low power dissipation hiccup mode. In
    the hiccup mode, the output drivers are disabled, the UVLO pin is momentarily pulled low, and the soft-start
    capacitor is discharged. The regulator is restarted with a normal soft-start sequence once the UVLO pin charges
    back to 1.23V. The hiccup mode off-time can be programmed by an external capacitor connected from UVLO pin
    to ground. This hiccup cycle will repeat until the output overload condition is removed.

    Regads,

  • 0 in reply to EricLee
    Prodigy 40 points

    Hi Eric,

    Thanks for getting back to me on this. To answer your questions;

    Power up with Vin = 10V

    Vss = 460mV

    Vuvlo = 2.9V but it also has a -ve going spike every 80ms. Sounds like hiccup mode.

    Vout (no load) = 4 to 7V

    Power up with Vin = 15V

    Vss = 1.4V

    Vuvlo = 3.6V

    Vout (no load) = 12V

  • 0 in reply to John Cameron1
    TI__Guru 58761 points

    Hi

    It looks like hiccp mode current limiting.

    Current limit is tripped easily when input voltgae is low and soft start time is short.

    A switching noise makes the current limit tripped earlier than expectation. Optimized layout helps to reduce the noise. Adding snubber on both Buck and Boost leg helps to minimize this noise issue.

    Regards,

  • 0 in reply to EricLee
    Prodigy 40 points

    Hi Eric,

    I understand your point about the noise and the layout, but I would like to experiment a bit further with the existing boards.

    Would you explain a little more about the snubbers please?

    Regards,

    John

  • 0 in reply to John Cameron1
    TI__Guru 58761 points

    Hi

    There are a lot of articles about Snubber on the web.

    In your case, you need two snubbers, one from the source connection of Q2 to the ground connection of R13, the other from the drain connection of Q4 tothe positive conntion of C18. Good starting point is 8 ohm (1W)  + 470pF (100V)

    Regards,

  • 0 in reply to EricLee
    Prodigy 40 points

    Thank you Eric,

    I will experiment and let you know how I get on.