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TPS77825 decoupling capacitors

Rob Mitrunen
Expert 1685 points

The datasheet is very clear on the output capacitance requirements - the ESR should be between 0.05 and 1.5ohm.  It is easy enough to find a capacitor to meet that requirement.

 

However, the load for this regulator is an IC that needs decoupling capacitors on its power pins (100 MLCs if I believe the datasheet!).

Now the LDO output sees the parallel load of all those extra caps, which will reduce the effective ESR way below 50mOhms.

 

Do I include those decouplers in the calculation of the effective ESR seen by the regulator?  Since they will be located close to the regulator, probably within an inch, and are connected between low inductance power and ground planes, I tend to think so.

 

In that case, is there some kind of compensation I can add to the LDO to mitigate the issue.  The obvious (and possibly naive) choice of a small value resistor between the LDO and the load seems inelegant to me.

 

Appnote SNVA167, which confirmed my suspicions is not helpful either. It suggests building a board and measuring the effect, but that is not practical for our timeline versus designing it right the first time.

  • 0
    TI__Guru 71526 points

    Hi Rob,

    Very good questions, and at this point I do not have a definitive answer, but will provide these guidelines:

    Since the load IC is located at some distance from the TPS77825, there is some series resistance in the traces and vias, effectively adding some ESR albeit small.  And since we are dealing with distributed capacitance, ceramic and electrolytic, the ESR is not simply combined as parallel resistance.  In terms of poles and zeroes in the compensation loop, this now becomes a complex zero/pole/zero situation.  Calculating or modeling the effect can give you a representation of what the loop looks like at the frequency of interest.  In general, as long as the electrolytic cap is large compared to the ceramics, there is probably not a problem.

    I believe we have some reference designs that employ this same predicament you are describing; I will look into this in more detail and provide additional information within a day.

    -Leonard

     

     

  • 0 in reply to LeonardEllis
    Expert 1685 points

    Hi,

     

    My customer is finalizing their design and has requested the additional information as soon as possible.

     

    Thanks,

    Rob

  • 0 in reply to Rob Mitrunen
    TI__Expert 3300 points

    Hi Rob,

    It depends on how close the decoupling caps are to your LDO output cap. The PCB trace can add some parasitic inductance that can decouple the resonating effect. To be safe a footprint for an inductor should be placed in between Cout and the decoupling caps. In case instability is seen, the inductor can be populated otherwise a 0 H Inductor can be used.

    Hope this helps. 

    Regards,

    Kartik