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UCC28950 active output drive anomaly at power-on.

Robert Legg
Prodigy 150 points
Other Parts Discussed in Thread: UCC28950

Shortly after power is applied and the reference of UCC28950 is established (~4mSec), output drive waveforms on A, B,C,and D are produced that are unexpected, based on the specified operation of the chip. They last for approximately two switching cycle periods. Though their phasing would normally represent a zero power transfer, no active high outputs are expected until the SS/EN pin is released. Both this SS/EN pin and the EA+ pins are clamped to ground during this period. The only other dynamic pin change, noted at the time of the unexpected output drive, is an alteration in the RT signal, which falls momentarily from Vref to ground before settling at Vref/2, due to internal IC  influences alone.

Your forum GUI does not appear to accept bmp or png images, or a pdf attachment with these images included, at this time. I trust that the description alone is sufficient.

 

legg@magma.ca

 

  • 0
    TI__Guru* 86266 points

    I have not seen this behavior before.  The good news is that it sounds like it does not produce gate drive waveforms that would cause the power supply to malfunction.  Has anyone else on the forum seen this kind of behavior with the UCC28950?

    Regards,

     

  • 0 in reply to Mike O'
    Prodigy 150 points

    In addition to the power-up-triggered output anomaly, I'm also seeing a phasing issue during an externally enforced slow-start.

     

    The EA+ pin is clamped low to disable, then allowed to capacitively charge to Vref (4u7 and 100K). The resulting first output drive shows the lagging phase to be 500nS ahead of the normal drive lead phase - resulting in an effective 10%duty at the operating frequency, when zero power transfer is intended. This gradually transitions through zero-power zero-phase difference to assume the normal lead/lag relationship.

    The same issue with inserting or attaching images. Will update previous link in the next 24hrs.

  • 0 in reply to Robert Legg
    Prodigy 150 points

    It appears that I've misunderstood/mislocated the leading and lagging drive identity on this assembly, and there is no issue. The 10% minimum duty at start is in the correct sense, in any event. It does not pass through a zero-phase delay situation.

    It is unaltered if the conventional SS/ENA line is used, with or without the external delay through EA+ being present, though for SS/ENA the first drive edge shows no delay between phases, only the subsequent edges.