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UCC28950 Power train stability and isolator volt-second balance issues under peak limiting conditions

Robert Legg
Prodigy 150 points
Other Parts Discussed in Thread: UCC28950

In this application, the UCC28950 is normally used as an unregulated full-bridge HV DC-DC switch controller. Slow start is used to reduce potential stress on switches due to small output inductors at start (or hiccough re-entry from limiting). The EA is only used to enforce a similar slow start under system reset requirements.

I find, however, that the CS reaction to peak current limit settings introduces major volt-second imbalances, as the logic switches from near-zero to full duty in half-frequency increments. This was demonstrated in one unit due to abnormally high internal slope settings triggering the peak detection early.

It looks like a peak detection in one phase period caused the following phase (alone) to be cancelled. Such a condition ramps the full bridge isolator into 3xnormal peak flux in a single event.

The currents generated under saturation are non-linear from one period to the next and are actually preserved under the zero-power-transfer protective phasing. In this application, a single missing period, generated by a peak detection seems oddly reinforcing.

Is there any way of making the peak current limit (ie a fault) enforce a definite SS cycle?

The usual problem with images here. Will follow up with link.

 

  • 0
    TI__Guru* 86266 points

     It sounds like you running this open loop and you have conditions where the transformer saturates. It almost sounds like you have the device setup in voltage mode control even though it open loop.  If you are using the device in this configuration you need a DC blocking capacitor before the transformer.

    You could setup the controller in peak current mode control.  You still should be able to control the duty cycle open loop.  You would just need a current sense transformer.  There is an application note for this device that shows how to setup the CT. The following link will get you to the application note.  http://www.ti.com/litv/pdf/slua560c

    Regards,

     

  • 0 in reply to Mike O'
    Prodigy 150 points

    The promised images are available at:

    http://www.magma.ca/~legg/TVS/UCC28950_peak_current_limit_DS0006_flux_reconstruction.pdf

    Your comments re method of control etc seem somewhat non-sequitur. Do you expect a control loop to counteract the effects of a peak current detection incident?

    Supposedly, such an incident occurs because the conventional control routine has not been able to avoid it........

    To be subsequently tossed into a non-recoverable chain of events seems a pretty poor idea of circuit protection (and possibly a misapplication of the method).

    One can, with the addition of external components, clamp the voltage control loop so that it reacts to avoid the CS half-cycle drop, however it is unable to react quickly enough, always, to prevent this pin from triggering. A further bunch of figures illustrates this kind of control and the effects of an extreme overload:

    http://www.magma.ca/~legg/TVS/UCC28950_reworked_for_voltage_control_130303.pdf

    Me thinks that, in configuring logic for a pulsed current limit, one that arbitrarily removes single subsequent conduction periods entirely (without receiving some kind of evidence that the overload is actually continuous), you'd need to keep better track of what you're asking the power train to do. Until that time, we'll continue avoiding influence from this particular protection scheme, thank you very much.