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TPS23753A gate drive logic interpretation (data sheet block diagram)

Daniel Godfrey
Prodigy 25 points

PoE Product Team:  

I am requesting an explanation of the logic that commands the gate drive, in part via the CS (current sense) input.   In particular, could you clarify the operation of the network that is shown in the block diagram on page 6 of the data sheet?  There is a 3-input NOR gate (single inverted input, and inverted output) that clears the D Flip-Flop which establishes the gate drive.  

With a normal NOR gate, the only time the output goes Hi is when all the inputs are low. With the inverted input, the only time the output goes Hi is when the inverted input goes Hi. The inputs are the enable (which I assume is Lo because if it is Hi then it disables the NOR gate), the output of the Control Comparator and the output of the Current Limit Comparator. The outputs of the comparators are active Hi. If the Control Comparator goes Hi, then it clears the D-flop because its output is the inverted input to the NOR but when the overcurrent comparator goes HI, I don't see it doing anything except taking away the clear signal which was activated by the Control Comparator. I must be missing something.  

Please advise,

Dan Godfrey


  • 0
    Prodigy 5 points

    Dan, I would look at what this should be doing.

    1. Oscillator output goes high, indicating start of a new PWM cycle.
    2. Clocks a 1 via the D FF input to the Q output
    3. 2 1's on the AND gate make the GATE output go high
    4. CTL sets the steady state feedback voltage into the - input of the 3 input PWM comparator, Comparator output is low because both - inputs are above the +
    5. current ramps up in the power stage, seen on the CS input, when CS causes the + comparator input to be above the - the comparator output will go HIGH
    6. this should CLEAR the FF via CLRB input and force a 0 on Q, thus turning the GATE output low

    7. There is a peak current limit comparator, 0.55V reference, whose + input is the CS signal. When CS gets above 0.55V this comparator output goes HIGH
        performing a CLEAR function on CLRB, thus turning GATE low terminating the present pwm cycle.
       

    8. ENB enable is the middle input of the NOR gate. ENB should be a high signal, so when LOW it should cause a CLEAR function on the FF.

    NOR:

    0  :  0  :  0 = 1
    1               = 0

    PWM comparator outputs 1 to CLEAR FF
    Overcurrent comparator outputs 1 to CLEAR FF
    ENB is a 0 to CLEAR FF

    Resulting Truth Table:
    0  :  0  :  0  = 1   enb = 0 causes FF clear
    0  :  1  :  0  = 0   FF ready to be clocked to start PWM cycle
    1  :  1  :  0  = 1   pwm = 1 causes FF clear
    0  :  1  :  1  = 1   OC  = 1 causes FF clear

    This looks like an OR gate with the middle input inverted (DOT).

    However this is really just semantics.
    Understanding the function of setting and clearing the PWM Flip Flop is the fundamental operation.

    I hope this helps.