In datasheet P.13, there is the NOTE about PGD pin.
NOTE
When there is no power to the device, PGOOD is not able to pull close to GND if an
auxiliary supply is used for the power good indication. In this case, a built in resistor
connected from drain to gate on the PGOOD pull down device makes the PGOOD pin
look approximately like a diode to GND.
Please teach me this description.
My understanding is the following.
1, In case of there is no power to the device, voltage is added to FET gate because the resistor is connected from drain to gate when PGD is pull-up condition.
2, So the FET becomes on condition. But drain is pulled down to GND.
3, FET turns off because drain voltage level drops.
4, Drain voltage level rises up, and FET turns on again.
5, Repeat 1 to 4 cycle.
For the above operation, low level voltage appears on PGD pin. According to my test, the level is about from 0.6V to 1.0V. (This varies depend on pull-up level.)
[Questions]
Is my understanding right?
What is the voltage level?
Why it becomes that voltage level?
Please teach me the purpose that there is a built in resistor from drain to gate.
