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TPS40304 Soft Start Feature

Adam Elias
Prodigy 100 points

Hello,

I'm designing a power supply to step down a voltage from 4V to 15V down to 3.3V.  I have the design in the lab working well, but I have an issue with the soft-start circuit where I believe the FSS resistor connected from EN/SS to BP is biasing the soft-start capacitor as well as the intentional 10µA current source.  This in turn is cutting my desired soft start time by at least 3, hence triggering the over-current upon start-up.  

Can someone verify that I am correct in this thinking?  With a 0.33µF capacitor on the EN/SS I expect ~20ms of soft start.  When the FSS 267k resistor is attached from EN/SS to BP this turns into ~7ms of soft-start.  

If this is the case, nothing is stated in the datasheet. I would expect somewhere in the datasheet to state, "Hey, if you use the FSS resistor use this equation for your soft start calculation"  I don't know the equation since I just simulated in SPICE instead to obtain my above example numbers.  

Lastly, the block diagram does not do a good job in showing the LDRV and HDRV over current sensing.   If I read the data sheet correctly this is a measurement of the VDS voltage on the upper and lower MOSFET during a switch cycle.  I'm taking it that is a measurement from VDD? - SW for the high side and SW - GND for the low side.  The block diagram doesn't show this well, and I can't imagine it being terribly accurate since VDD could be pretty far from the high side MOSFET.  The low side MOSFET should be a little a more accurate.

Thanks,

Adam

  • 0
    TI__Genius 17240 points

    Hi Adam,

    Sorry for the confusion. You are right that the pull-up current from BP to EN/SS with the existence of FSS resistor will lead to shorter soft-start time. When the input voltage is above 6.5V, the soft-start time will be cut short to ~1/3 of the calculated value. When the input voltage is 4V, the soft-start time will be cut short to ~1/2 of the calculated value.

    You are also right about the high-side and low-side current sensing. The high-side sensing is based on VDD-SW voltage and low-side sensing is based on SW-GND. So the VDD should be as close to the drain voltage of high-side FET as possible for better current sensing accuracy.

    Regards,

    Na

     

  • 0 in reply to Na Kong
    Prodigy 100 points

    Thanks for the response and confirming what I was seeing in the lab and in my simulations.  

    Any plans to get the datasheet updated to prevent future frustration by designers who select this part?  

    ADam

  • 0 in reply to Na Kong
    Prodigy 10 points

    Na,

     

    I too have a question for soft start.  What is the calculation for soft start time.  We are designing a 12V input to 1.7V+-0.2V adjustable output at 11Amp.  We need a slow start for this application. Heating element and cable are resistive load from 140ohm to 160ohm after wire and heating element warm up.  We have an ACDC wall wart 18W (27W over power trip setting) that is tripping over power condition for cold start.  I am hoping to use the DCDC soft start to alleviate the problem.

     

    All ideas are appreciated.

     

    Brian T

  • 0 in reply to brian truesdale
    TI__Genius 17240 points

    Hi Brian,

    During soft-start, the DC-DC does not only provide the load current (11A), but also the charging current for the output capacitors. The average charging current is

    Icharge = Vout*Cout/tss, where tss is the soft-start time set by the soft-start capacitor (equation 1 in the datasheet)

    Based on the current limit you have, the soft-start time can be set to give enough margin for the inrush current during start-up, i.e.

    (Iload + Icharge) < current limit, so you can back calculate the soft-start time and soft-start capacitor value. Hope it helps.

    Regards,

    Na