I was just going back over a design and I was reading the OCP and SCP (Overcurrent and Short Circuit Protection) section when it occurred to me that the blanking interval that the chip samples the SW voltage after switching on HDRV or LDRV is never specified. I wanted to use it to see if the small amount of ringing on the SW node was OK or excessive. The datasheet does say to minimize the ringing (obviously), but what is acceptable? Does the chip sample after 10ns, or 100ns, or what?
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