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TPS7A4501 LDO shutdown pin supported IO voltage logic

swapna bramandlapally1
Prodigy 170 points

Hi,

I am using TPS7A4501 LDO in my design.I want to control the LDO output using Shutdown pin from FPGA.

In datasheet no where it is not mentioned supported shutdown pin IO logic.

What is mean by shutdown threshold voltage.Is this any correlate with shutdown pin IO logic.

Can somebody explain this.

Thank you,

Regards

Swapna.B

  • 0
    TI__Expert 3300 points

    Hello Swapna,

    Thank you for your post. Page 2 of the PDS gives the absolute maximum ratings which show that up to +/-20V can be applied to the Shutdown pin. I believe this covers all logic levels for any digital logic.

    The threshold values in the PDS give levels at which the Vout will turn off and on. For example when going from high to low on the SHUTDOWN pin, typically at 0.9V (max 2V), the output will turn on.


    Hope this helps.


    Regards,

    Kartik