• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 65 subscribers
  • Views 471 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Power Sequencing with multiple TPS62130 and TPS53319

Peter Watson
Prodigy 230 points
Other Parts Discussed in Thread: TPS62130, TPS53319

Hello,

The controller I am using on my board requires that the five differnet voltages powering it power up one after the other.

First, the +3.3V generated by a TPS62130

then +2.5V generated by another TPS62130

then +1.2V generated by a third TPS62130

then +0.8V generated by a TPS53319

and last +0.67V generated by a second TPS53319

 

To meet this requirement, for each voltage regulator I connected the "Power Good" pin to the "Enable" pin of the following voltage regulator. (SEE ATTACHED SCHEMATIC FOR DETAILS) 

But now I am facing the problem that the PG pins of the TPS62130s indicate "Power Good" even though the corresponding voltage regulator isn't even enabled yet by its preceding voltage regulator. Why is "Power Good" (high-impedance) indicated by the device if the output voltage is still 0V?

 

How can I solve this problem and make sure that one power powers up after the other?

 

Thank you very much for your help!

Power Sequencing.pdf
  • 0
    TI__Guru**** 150640 points

    This is the correct operation of the TPS62130 device.  You have a few options to adjust it:

    Pull-up each PG pin to the output voltage of the particular converter.  Thus, when that converter is off, the PG will also be low as there is no pull-up voltage.  This won't work for the 1.2V output, as that level is not high enough to turn on the next TPS53319 as its EN pin logic level is too high.

    You could add a schottky diode from PG to the EN pin.  Thus, when EN is low, PG is also held low through the diode.

    Instead of sequencing this way with the PG and EN, you might add an RC circuit from PG to EN to give additional delay time.  This would keep the downstream circuit off for additional time, while the previous circuit has enough time to finish soft start.

    Finally, you can contact your local TI or distributor FAE who might know of some other tricks.

  • 0 in reply to Chris Glaser
    Prodigy 230 points

    Wow, that was fast :-)

    Thank you very much for your reply.

    I am kind of confused: How could anybody design a voltage regulator, that indicates "Power Good" when the output voltage is far from being good?

    Is this also the case for the TPS53319 or does this device work properly and keep the PGOOD pin low until the output power is good? 

  • 0 in reply to Peter Watson
    TI__Guru**** 150640 points

    I will let the appropriate engineer reply regarding the TPS53319.

    Note that the TPS62130 only indicates power good because it is off and because you pull up the PG pin to a different system rail.  This may not be a typical configuration.  Many customers assume that when a device is off/disabled, that it is completely out of the circuit.  This is the case with this device.  If you turn it off, it goes high impedance.

  • 0 in reply to Chris Glaser
    TI__Guru**** 191445 points

    It is not entirely uncommon for that type of PG behavior.  I think the thought behind it is to decrease power dissipation in standby (not switching) operation.  When the device is disabled, the PG pin is not actively sinking current.  It is thought that the EN is under user control, so he knows that power is not good when EN is low.  You can do as Chris suggests and pull PG up to a voltage that is not present when the device is inactive.  Or possibly AND PG and EN.

  • 0 in reply to Peter Watson
    TI__Mastermind 49370 points

    Hi Peter,

    TPS53319 works properly and keeps PGOOD low until the output voltage is good as long as EN is higher than 1.6V(EN start up voltage 1.3VTyp, 1.0Vmin and 1.6Vmax). In addition, the internal PGOOD MOSFET is powered through the VDD pin, the VDD must be higher than 1V in order to have a valid PGOOD logic. Usually it is recommended to pull PGOOD up to VREG. So that the PGOOD logic is still valid even without VDD supply. Please refer to datasheet page 19.(PGOOD section).

    Thanks,

    Nancy