Hi.
I am experimenting with the TPS63700 EVM 5V in -12V out.
I got the following unexpected behaviour:
1) At >=5V input and no output load applying a sufficiently high dV/dt input voltage (it is sufficient to use a bench power supply and connect the EVM when the PS is turned on) latches the IC in a state where substantial (0.5A up to 1A) input current is taken without any switching. A first EVM was damaged due to overheating the IC, I bought a second and it does the same, I saved it by putting a low current limit on the bench power supply. The problem is solved by slowing down the rate by using a 470uF capacitor at the input connections of the EVM.
2) The IC under certain conditions latches in off state and is resumed ONLY when the input power is cycled. The conditions are overload, short circuit. Latching off means that if fault is removed, the IC does not resume operation. There are several unanswered questions about the same problem on the forum, one of which is "Why the IC latches off?" Where is it written on the data sheet? The only useful information is that the IC has problems if started up with negative voltage on the output. Which is not encouraging... i.e. repeated startup: the second one will find a negative output voltage.
3) in few occasions I saw the output voltage going to -27V with no load. I cannot reproduce it easily but it seems related to the latching problem 1)... sometimes it latches for a while then resume but generating -27V.
Problem 1 and 3 are really a no-no. Hopefully in real application the input voltage will rise slowly.
Problem 2 makes me think that the IC will be able to deliver no more than 1W output, even if the datasheet reports up to 3W (-15V @ 200mA).
I repeat, I used the EVM so there is no argument about customer implementation errors.
