TPS3808 timing capacitor question

Scot,

I had a customer ask a similar question.   I used your answer for first pass reply.

However, it sounds like they are wanting to quantify any errors with respect to the delays.   Do we have any approach to quantify the errors in delay?

First question would be silicon alone, then what would the contribution be from capacitor tolerance.

My first reply indicated to use the graph, then apply the tolerance from capacitance from the equation.

My first reaction, is that they are trying to use this device with more precision that design intended.  Could you comment?

Unfortunately (as usual), they are on a short fuse and would like answer ASAP.

Thanks.

Regards,

Wade

We don't individually quantify the error terms for the delay.  The aggregate error is reported as the min/max values.  The min/max values do not include the tolerances of external componenets (such as the timing capacitor tolerance and temperature coefficients).  You are correct that this must be added on top of the the range shown in the datasheet.  Generally speaking, voltage supervisors are not meant to be precision time circuits but are only meant to generate a reset for a microcontroller.  If they are worried the reset signal is too short, then the usual solution is to increase the nominal reset time.  The only impact is the microcontroller stays in reset a few exta milliseconds.

Scot, Thanks.

Is there any data that could be used to bound the delay for a specific capacitance/vcc value?

I think they are trying to bound the min/max range for their specific conditions.   Not sure how much of an influence the large VDD range has on the variability of the delay.

Regards,

Wade