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I have forwarded your request to the PMP6776 design engineer. He will try to answer later today.
Hi Ryuji,
The timing sequence of PMP6776 is designed according to the following spec:
"
Sequencing on the power module will be required to be compliant with Kintex 7 specifications. 1.8V (Vccaux) must come up first, followed by 2.0V (Vccaux_io), then Vcco. The key to this sequence requirement is that Vccaux must reach its final regulation voltage before Vccaux_io can exceed Vccaux. Likewise, Vcco cannot exceed Vccaux_io until Vccaux_io reaches it’s final regulation voltage. Based on this requirement, tracking the supplies is also permissible as long as Vccaux is not exceeded by Vccaux_io and Vccaux_io is not exceeded by Vcco during initial ramp.
Each supply must ramp monotonically between 20-50ms. Because the startup time is so slow, the inrush current from starting supplies simultaneously should not be an issue. "
Hope that's helpful.
Regards,
Sheng-Yang Yu
Hi
what about VCCINT & VCCBRAM ?
according to the Kintex 7 specification those two rails have to be set first .
VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO
Best regards.
Paulo.
Yes, the sequence of Vccint & Vccbram (1V) > Vccaux (1.8V) > Vccaux_io (2.0V) > Vcco is designed in PMP6776.
Please see the PMP6776 test report page 3 as follows:
http://www.ti.com/lit/ug/tidu046/tidu046.pdf
Regards,
Sheng-Yang Yu