TPS79930DDC LDO minimum output current requirement....?

Hi,

Thank you for your post. The TPS79930 will be stable with < 100uA load however the output accuracy is guaranteed only starting from 500uA but in sleep mode, this is not important to you. 

Please note, your maximum current is 280mA whereas this LDO is designed to source 200mA. On some parts you may hit current limit in which case you will not be able to get up to 280mA and if this adversely affects your system, then you should take a look at LDO's can source more current under normal operation.

Going from almost no load, to 200mA+ will lead to larger settling times and possibly larger overshoots, using a 10uF output cap will lead to less of overshoot and you will have to account for the settling time. Hope this helps.

Regards,

Kartik

Hi,

Thanks for the answer.

There is a small typo here, the maximum Current taken by FEM when Power amplifier was saturated is around 230mA not 280mA as mentioned in prev post, which exceeds the 200mA current limit of the IC.

But the TPS79930DDC 's current limit has 3 values

min -200mA

typ- 400mA

max - 600mA

1. under what conditions typ and maximum values can be considered.

This is also not an issue. Problem is when we are entering into sleep mode the current consumption is 157uA.

Total current calculated worst case is =70uA, there is a differnece of 90uA. 

2 .is there any possiblity that this additional current (90uA) is taken by the internal circuitry of TPS79930DDC.in addition to ignd of 40uA?

There is no other element connected to this rail.

Please let me know if i am not clear.

Hi,

1. The current limit spec is like any other spec on the PDS which has a lower, upper and typical limit. What this means is that different parts will have a different current limit value, some will hit current limit as low as 200mA, some as high as 600mA, but based on our characterization, a majority of the parts hit current limit at ~400mA. There are user no conditions which influence the current limit value, just process variations.

2. Can you please share your schematic? This will help me help you better. However, the Iq is the urrent being consumed by the internal circuitry of the LDO. If your load is drawing 100uA, then the Vin pin of the LDO will pull Iq + 100uA from the power supply. So in your current consumption you have to take the load into consideration. Only when there is absolutely no load (open circuit), the current consumed by the LDO will be approximately 40uA.

Regards,

Kartik

Hi ,

thanks for the answer.

As i mentioned on first post, i included this iq of LDO into the calculation.

I can't share the schematics, But, i can give more details.

THe loads connected to LDO are

1. OR gate - upto 30uA it can take in sleep

2. FEM (SE2431L) - max of 1uA

3. BC847 - Icbo of 10nA

They all comes totally about 32uA, but current measured from LDO input is 157uA. So, if Iq of LDO is removed from total current (157-32-40) = 85uA is somewhere consumed( we feel this can be consumed by LDO internal circuitry).

can you give comments on this.

Hi,

The max spec for Iq is 60uA so it is unlikely that the LDO's internal circuitry is drawing so much current unless the part is damaged. Have you tried the following:

• Isolating the load and measuring the current draw by the LDO when nothing is connected to the output? 
• Trying a different LDO unit to make sure the one you are using is not damaged?

Hi,

These days i am not feeling well. 

I have received the samples today. I am going to test the LDO and  post the results.

Regards,

Malli

Hi,

Thanks for the co-operation.

I have tested this LDO sample on General purpose board in No-Load and with very less load combinations.

It takes around 46uA of Quiescent current -this spec is almost as per the datasheet.

In our circuit, even i have measured individual currents going into FEM, BC847N in sleep mode. they are as per datasheet specs. Because OR gate is QFN package i can;t able to measure the current it takes.

t hs a 

one input state(nFEM_SLP) of OR gate is unknown. may be floating creating doubt. unfortunately it was routed in internal layers. 

if you see any discrepency please let me know.

Do you have leakage in your board?