Hi.
We're designing a +24V to -48V DC/DC power supply based on the LM5116 controller, and are using LM5069-2 for handling UVLO and inrush control into the DC/DC. We've connected the PGD pin from LM5069-2 via a transistor network to the LM5116 UVLO pin. So if the PDG pin on the LM5069-2 goes low, it will immediately stop the LM5116 controller.
We see that when we create an UVLO event under high loads (+24V supply is adjusted below the UVLO threshold (around 16V)), the PGD pin drops immediately. But it doesn't trigger any kind of timer delay. The PGD pin goes high again only after only 200us. This even though we have a 0.5V hysteresis on the UVLO. So the result is that the DC/DC ends up cycling between on and off, at a frequency set by the LM5116 SS capacitor (every 200ms or so...). How do we get the UVLO event to trigger a timer delay?
Best regards,
Øystein Johnsen.
