My design currently links the output of the LM5010A to the input to the LMR62014 as shown in the schematic snippet attached. This topology seems to work well using the evaluation boards. However, I am concerned about the LM5010A's specification concerning minimum output ripple voltage (and minimum ESR through the output capacitor). If TI can critique this topology and provide guidance on the reliability of this topology, and whether any layout considerations are needed to make a more robust design (e.g.locate C56 a minimum distance from C13/R54) that would be appreciated.