TLC5940 / TCL5941: glitches when shortening the PWM cycle

Hi,

I'm very interested to know the answer to this issue as well.

Thanks, Jon

Hi Jon, unfortunately no new information ... the problem is pretty clear and repeatable, as the clock speed goes up from around 12Mhz the PWM dropouts happen more and more often.  I'm getting identical behavior on 5 boards.

I can only assume there is something wrong with how I'm using the chip, but as you can see there is no info/help from TI and I've spent 2-3 days on it and I'm done.  For the next design revision I'm going to suggest to my client to spend some money for me to design out the chip and either use a macroblock part or a tiny fpga.  Because of this issue I can't get the PWM refresh rates I've promised, the client may or may not care.  I'd rather just fix what I have but unless someone from TI steps up here it is a dead end.

TI you'll lose $10K in sales on this issue to my client for sure, and all future design work I do for anyone will use macroblock (or whatever) instead, as well, of course.  I can understand that isn't enough to care much about just $10K but you're no longer on the train...

J

 Hello Jesse,

Could you check the following points?

1. What is setup time of BLANK falling edge to GSCLK rising edge on your system?

     BLANK signal must be set low at least 10ns earlier than 1’st GSCLK rising edge.

2. Is GSCLK clocking held while BLANK is high level?

     If GSCLK clocking is not held, could you try to hold the clocking during high BLANK.

3. Is XLAT high pulse input for GS data writing input during high BLANK?

     XLAT high pulse for GS data writing must be input when BLANK is high level.

Best regards,

Kazuya Nakai.

Hi Kazuya, thank you for the reply.  I have looked into this further.  I'm using a PIC microcontroller running at 10 MIPS, typical of the inexpensive microcontrollers the TLC5940/1 is designed to operate with.

The GSCLK for the TLC5940 comes from an external oscillator, since it is not possible to generate anywhere near 30Mhz with a low-end PIC, nor a msp430, nor anything else.  The PIC 18F line can generate 8Mhz via PWM hardware at best.  Therefore, in order to use the TLC5940 at high speeds with ANY lowcost microcontroller, the GSCLK signal must be externally generated and externally gated.

This is the core of the problem.  Due to the TLC5940's requirement for this main PWM signal to be held during BLANK, and for setup times of other signals relative to it, it is a difficult nuisance to use it effectively.

What I'm doing is using an AND gate to gate the external OSC clock with a PIC gpio output so that I can shutoff GSCLK when I'm doing BLANK/XLAT signaling.  This simple method has now been proven insufficient.

I am able to achieve all three of your points with this design, but as the extern OSC clock speeds go above about 12Mhz, the PWM 'dropout' glitches get worse to the point of unusable.

As a test, I added the following logic to the firmware.  After the PIC counter interrupt fires (every approx 1000 GSCLK pulses), I now do this:

1) wait for GSCLK to go low, if not already

2) wait for GSCLK to go high

3) wait for GSCLK to go low

4) now gate-off GSCLK with the PIC GPIO pin wired to the AND gate.

This results in far fewer glitches, like 1/100th as many.  By enabling and disabling the above code I can clearly see how much better it runs.

Why?  because the AND gate and the PIC GPIO pin are not (and cannot be) synced with the external oscillator, so runt pulses are occasionally generated as the AND gate closes and opens with the PIC GPIO.  This apparently creates bad internal states in the TCL5940.  Adding firmware that attempts to sync the gate-off with the external oscillator phase helps this (a lot).  Unfortunately with the hardware I have I cannot do the equivalent sync to re-enable GSCLK, which may or may not explain the infrequent remaining glitches.

This technique also doesn't work past about 16Mhz for the external oscillator since the PIC (like any low-end microcontroller) doesn't run fast enough to meaningfully monitor inputs faster than this.

So in order to use the TLC5940 at anywhere near is design capacity with the kind of microcontrollers it is intended to work with, a substantial amount of glue logic is required.  I have a paper design with an AND gate, inverter, and two flip-flops that I believe will work to make it so that the GSCLK gating on and off happens cleanly.  This adds another chip to the design, beyond the AND gate chip I already have (which will become a larger dual NAND to perform the AND function and the invert function).

I'm disappointed that TI designed a chip that requires this much glue (actually, ANY glue) to work with a typical microcontroller, and has caused such hassles for me and anyone else trying to run it flawlessly past simple lowspeed (4Mhz) PWM clocking.  Even at the lower speeds, with GSCLK being generated by the microcontroller running the show, a microcontroller hardware counter and careful firmware coding is required.  All of this comes from the requirement that GSCLK be gated off while clearing/reloading the PWM settings for the channels.  Other chips by other manufacturers don't have any requirements like this.

Thank you for your help.

J

 Hello Jesse,

  I think the GSCLK pulse width gated by AND might be shorter than the minimum pulse width spec (16ns) of GSCLK. Could you try to check the gated GSCLK pulse width?

 Best regards,

Kazuya Nakai.

Hi Kazuya, there is no way for firmware to ensure the AND gate won't generate < 16ns pulses when GSCLK is running at higher speeds (12Mhz+).  I expect to implement my 2 flipflop + inverter + AND gate solution in the next revision of the client's design, which is beginning happening next week.  I'll report back if it works, or not, and if it does work I'll try to add a picture of the schematic so other people can do it to avoid this issue.

Thanks-

J