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bq77908a charger detection CPCKN design

Konstantin Nickel
Prodigy 90 points
Other Parts Discussed in Thread: BQ77908A

Hi guys,

I actually have problems designing a charger detection for the bq77908a. The one I built is sending out a pulse to CHGST every time the Pack(-)  terminal gets defined. Problem thereby is that I run the system in series FET configuration for lower space consumption and need to pull down CPCKN when the system goes in shutdown mode (datasheet page 32). This pulldown defines my Pack(-) terminal again and lets my charger detection wake the chip up again. Consequently it's swinging on and off all the time when it should be in shutdown mode.

Now I have 2 pleases to you. First one is to explain me detailed what DPCKN and CPCKN do and how they work, because it's very confusing to me what's written down in the datasheet about them. All I know so far is that these pins have something to do with the load detection. My first idea to solve the problem above was to put a diode between CPCKN and the Pack(-) terminal for releasing the Pack(-) terminal from the pulldown, but I think this would have influence on some chip safety functions, right?

The second one is to tell me how I can use the CPCKN pin for charger detection as offered on page 9 of the datasheet.

I really appreciate your help!

Best Regards,

Konstantin Nickel

  • 0
    TI__Guru 54715 points

    DPCKN (Discharge PaCK Negative) is an analog input with a comparator to provide a digital signal to the part so it can determine if a load is detected. See the datasheet page 4 block diagram.  DPCKN also has a weak pull down which along with the power FET leakage current will pull down a floating discharge pack negative pin so the part can determine that the load is gone.  RLDRMDET will also pull down if used, but is a more identifiable leakage path with a continued load after discharge protection.

    CPCKN (Charge PaCK Negative) is the sense for the charge FET source terminal; it is basically the negative power supply of the push-pull CHG pin driver.  See the general concept in the datasheet page 4 block diagram, or the diagrams in www.ti.com/lit/slua612 .  The charge driver can be a floating driver within the limits of the IC.  For parallel FET circuits it swings from Vss to some voltage below, for a series FET circuit it can swing below and above Vss.  There are effects on the IC power as the driver and level shifters work to resolve signaling between the floating driver and the main logic section of the IC.

    The 2 signals become related when series FETs are used with the floating driver.  DPCKN senses the pack negative voltage through the charge FET which has its source as pack negative and connected to CPCKN.  Also RLDRMDET becomes more important for series FETs since the resistor must help start up the floating charge driver after pack negative (and CPCKN) has been pulled to pack positive

    If you have a particularly dynamic system, or one where you need careful supply current control, or a very large charge standoff range, you may want to "ground" CPCKN to VSS and use the CHG signal to control an external charge FET gate driver of your own design.  You can design your driver to have a voltage tolerance larger than the IC to deal with transients or very large over-charge voltages.  Having CPCKN at ground will minimize shutdown current in the IC.

    Just as CHG could be used as a digital output, DPCKN could be controlled by a digital source such as a microcontroller, comparator or other logic in the pack.  This may be useful if you want a more sophisticated load recovery mechanism or have a system where pack negative does not change voltage quickly on current protection to allow load detection.

     A diode between CPCKN and Pack- may not be too bad since you want these to stay at about the same voltage except during transient event limits when you are protecting the IC.  If the voltage becomes too large you could turn on your charge FET when it is undesired.  A common interest is to keep CPCKN from moving too far above or below VSS, but if it is limited, CHG is similarly limited and the gate voltage may turn on the FET when a large charger voltage is applied or damage the FET (and possibly the IC) when a load is applied in an under-voltage situation.  Do check your design thoroughly for safety concerns.

    There are no present options available to use CPCKN for charger detection.  The part has the basic function of forcing VREG on when CPCKN goes sufficiently below VSS as mentioned on page 27 of the datasheet, however there is no parametric specification associated with this so a part could have a very different behavior and be considered good. If you do use this behavior, CPCKN going below VSS would raise VREG which would need to cause some circuit of your own selection control the CHGST pin.