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A question about the initial value of bq33100

Other Parts Discussed in Thread: BQ33100, BQEVSW

To whom it may concern,

I'm trying to evaluate bq33100 with EVM. When the EVM is powered on, some initial values are different from the Doc. of bq33100.

After being powered on, the function that automatically turning off the pin of CHG FET does not work unless FET Action is set.

So does the Fault pin.

Thus, if bq33100 is designed with a system of FPGA, the entire protected function is shut down and will not take action to harsh conditions, such us Over Voltage or Over Current, at the first time before the system set corresponding bit to turn on the protected function. What should I do to avoid this situation? Do I have to design a external circuit to limit the voltage and current to prevent the hazard?

Regards,

Gang

  • Hi Gang, 

    What function to turn of the fet are you referring to? When the device is turned on, the fet is automatically turned on. For evaluation purposes, if you need to turn off the fet, you have to go to the pro screen, and then write SMB Word, SMB 46 Word 0000. to turn back on SMB 46 word 0006.

    What function are you referring to with regards to the fault pin. The over voltage and over current protection features of the device are functional.

    thanks

    Onyx

  • Hi Onyx,

    Thanks for your fast reply.

    I prefer to turn on functions, which can turn off the charging circuit and report errors automatically while hazards occur, as a default condition.

    Because, the fault pin did not been triggered at the first time I use the EVM.  Due to the default value (0x0000), a corresponding value of Fault (Subclass ID 64 Offset 8) must be set to let FAULT pin (pin 15th) assert high while any violation happens. It means that if bq33100 is designed working with a FPGA system, the harsh condition will not be detected until 'Fault' has been set.

    The same situation happens to CHG FET either. Even if the OperationStatus [LTE] is asserted in normal mode, CHG FET will not automatically drive the CHG pin (pin 23rd) to shut down the charging circuit while a fault condition occurs. The reason is that FET Action (Subclass ID 64 Offset 4) must be set correspondingly to respond faults, such as OV, OC or SC, before it begin to protect the charging circuit of Super Capacitors.This automatic function that shuts down the charging circuit according to fault condition, does not be turned on as a default value at the first time that bq33100 is used.

    However, OV or OC might happen before FPGA sets 'FET Action' and 'Fault'. There is a widow that bq33100 detects the abnormal condition, but the information cannot be known by the FPGA system, because the system does not turn on corresponding functions to report errors. Furthermore, bq33100 cannot turn off the charging circuit itself neither due to the default value of 'FET Action'.

    Thus, do I have to design an external circuit, which can limit the current and voltage for the charging circuit, to prevent the hazard? Or can you provide a solution for this condition?

    Regards,
    Gang

  • Could anybody help me with this problem?

    Or the discription is not clear enough to be answered?

    Thanks.

     

    Gang

  • Gang,

    As  the device currently is, the safety status register is what gets set during a fault conditon.  Additional circuitry will need to be incoporaed to turn the charge fet off.

     

    thanks

    Onyx

  • An alternative will be to set the bits of the particular fault that you need the chg fet or fault pin to react to in  the FET action or Fault register. This way if there any of these faults occurs, the charge fet or fault pin gets to be driven high.

     

    thanks

    Onyx

     

  • Onyx,

    Thanks for your help!

    Gang

  • Hi Onyx,
    I have other two questions for you.
    1. After I power up the BQ33100, the BQEVSW tool can't detect the correct capacitance. Why?
    2. is there a way I can manually start a learn processes?

    Thanks,

    Tony
  • Hi Tony,

    Capacitance is only measured at the programmed learning frequency (see page 42 of the datasheet), or if it is commanded to do so with the 0x23 or 0x25 MAC commands (See page 23 of the datasheet).

    In order for the cycle to work, please insure that the various charger voltage levels are set to the values of your charger, or the EVM charger. The EVM charger voltages can be found in a table on the schematic.

     

    Regards,

    Doug

  • Hi Doug,

       Thanks. I did sent 0x23 command, but I need to wait about 4 mins to get capacitance updated, Is it right?

         what is the purpose of CB threshold? is it the voltage on each capacitor?

    Thanks,

    Tony

  • Seems a little long. The longest wait in the process is letting the caps settle completely at the upper charging voltage. I typically see just a couple minutes max. Are you using the EVM or your own target board? What is the value of the capacitors?
    CB threshold is the max delta voltage between all the caps where you would like to initiate the balance algorithm.
  • I did it on our board, not on TI's EV board.
    we have two 200F caps in series.
    If our charging voltage is 4.5V , so the BQ33100 will start capacitor balance at 2.25 +/- CB threshold. right?
  • Hi Dong,

         1. Which bit in operation cfg register is for RSOCL? I can't find it in data sheet.

          2. How the change level is calculated?

          3. Which condition does the capacitor considered as FULLY charged?

          4.If my charging level is hold at 99%, is the capacitor is bad?

    Thanks,

    Tony