I'd like to simplify the interface of the TLC5926 to two signal lines: SDI & CLK.
I will tie /OE to Vdd, and not attempt to read SDO.
May I tie LE to CLK? The application note http://www.ti.com/lit/an/slva346/slva346.pdf strongly implies this will work for the 5926. I understand that the OUT's will be delayed 1 clock.