TPS54620 Spontaneous shutdown and restart

Is that bottom waveform your steady state operation?  It looks unstable to me.  That aside, the inductor value seems very large.  Current mode control performs better with relatively larger inductors.  You compensation is not true type 3 with C352 unpopulated.  I would put at least 10 - 22 pF there.  I always get nervous with external clock.  I prefer to terminate RT locally with the R value that produces the same internal frequency as your external clock.  I always run a separate buffered clock output to each IC.  I don't directly support TPS54620 but have quite a bit of experience with it.  If I get some spare time I may model your compensation.

The compensation has been calculated with this xls-sheet: 2273.3V3 TPS54620_TPS54XXX_App Note_calculator_Ver5p0.xls.

 According to the sheet C352 should not be necessary.

The bottom waveform is steady state. Indeed it seems the regulator is skipping pulses. This subharmonic oscillation seems to be less with C391 removed. Only skips 1 in every 5-6 pulses. Is this cause for concern?

There are lots of ways to derive feedback compensation.  I personally prefer and recommend pspice modelling.  That spreadsheet will work for may applications, but it is a fairly simplified method.  I always try to get a completely uniform pulse train on the switching node for steady state operation.  While C352 may mot be necessary in an ideal case, I find it does help to attenuate noise in the control loop as it provides a direct ac coupling path to ground as well as adding a pole to the compensated error amplifier.

All this may or may not be related to your shutdown condition, but I think the first step is to get a completely stable circuit, then move on to the shutdown.  I happen to know the original IC designer.  I'll see if he has any comment about it next week.

Hello - A few thoughts: 

• It seems there is an external synchronization clock but no RT resistor. Is it possible that the clock is dropping out for whatever reason? The RT pin is very high impedance. I'd recommend adding a local RT resistor to each TPS54620 device, even if the synchronization clock is to be used during normal operation
• As john mentioned, there is some pulse-skipping/ pulse-width jitter at steady state, before the shutdown event, which you'll want to take care of before the shutdown issue can effectively be debugged. Two suggestions here:
  • Try a lower bandwidth loop. The designed crossover frequency of 70kHz is a bit aggressive for a switching frequency of 200kHz, though it should be theoretically possible. The equations in the spreadsheet, and the small signal models do not consider aliasing effects, which become significant at fsw/2 -- so you'll want to keep the crossover of a real system far enough away from fsw/2. You may want to try a lower loop bandwidth like 20-40kHz, even if its just for debugging to rule out whether that is causing an issue.  The datasheet recommendation for crossover frequency is 10% Fsw. 
  • Try using a smaller inductor. The inductor values seem a little large to me. One thing I've run in to with peak current mode control devices (such as TPS54620), is that the peak and valley current need to be sufficiently "different," otherwise the application design is more prone to pulse-width jitter. Using a large inductor makes the inductor ripple current small, and hence moves the valley and peak currents closer to each other. My thought is that 10-15uH is probably OK for this design, but it's something you'll want to verify. The datasheet also recommends that the inductor ripple current be 20-40% of rated current, which is 6A for this device. 

Yes if you check my first reply to the original post, I commented on the large output inductor and lack of RT termination.  I think that could well play into the stability issues, but I am not convinced it can cause the device to shutdown and discharge SS.

The board has been stable for more than 56 hours. So that's good.

I confirmed that only the 3V3 suffers from pulse-skipping. Tomorrow I will try a 15uH coil instead of the 22uH. I will also recalculate the type III compensation for 30 kHz fco, and also try that tomorrow.

I would still very much like to find an explanation for the shutdown/restart if possible.

Thanks for all the help/advice, it is really appreciated.

I talked to the IC designer.  He is not aware of any additional fault conditions that could cause the IC to reset.  Let me know if you have any additional shut down occurances.  If it does turn out that instability is causing the problem, I'll see if we can find an explanation for it. 

Changed the 22uH of the 3V3 and 5V supplies to 15uH. 

Type III compensation calculated with the App_note calculator:

fco (kHz)     30
R4 (kOhm) 8.1      =>  8k1
C4 (F)       3.0E-8   => 33nF
C6 (F)       1.2E-11 => 12pF
Cc (F)       1.6E-10 => 150pf

Confirmed that pulse skipping and sub-harmonic oscillation have disappeared. 

I also recalculated the compensations of the other 54620 power supplies, with an fco of 30 kHz.

After changing the components on the same board as I used for the previous tests, I also performed load-step measurements (load-step 5v/3v3:3A 1v2/1v9:1.5A) on all supplies 

green: voltage on load            yellow:ac coupled output of 3v3 regulator

The behavior of the other regulators is comparable.

I will report back tomorrow morning if the board has been stable for the night.

The calaculateor should work ok as long as you keep Fco low.  I think 30 kHz sounds reasonable.  Let me know if you have further issues.

Unfortunately another issue. When testing the system to -46 degrees celsius, we again saw the same shutdowns. And although I took the same measurements Tuesday with this same board (only difference is I lowered the clock frequency to 200kHz, instead of 220kHz), I again see subharmonic oscillation on the 3v3 supply.

purple: switch node, blue: 3v3 out, green: compensation

When I remove the Cc capacitor of the Type III compensation, the compensation stabilizes, and the 3v3 no longer skips pulses. Also then the board doesn't shut down at low temperatures. Next week I'll recheck with another board to rule out other issues, but I find the coincidence of the 3v3 giving problems yet again too much of a coincidence.

Questions:

- If I understand correctly from the app-note calculator, the only difference between the type II en type III compensation calculated with the xls-sheet is Cc. Are there drawbacks when using the thus calculated type II comensation?

- I today noticed that I entered the R8/R9 values somewhat different than as described in the app-note. I entered R8 as 31k6, to get a R9 of 10k. Can this be causing problems?

- Any other ideas?

The calculator appears to be off line, so I could not check it.  I assume Cc is the parallel capacitor from COMP to GND.  That capacitor provides a roll off pole that is useful for attenuating high frequency noise in the feedback loop.  I find a small value capacitor 10-22 pF usually helps to prevent "bi-stable" or "short pulse / long pulse operation".  The TPS54620 is only rated for operating temperatures to -40 C,  At cold temperatures, one thing to check is placement and routing of the input bypass capacitors.  Proper placement is important for stable operation.  The feed back resistor values aren't too important as long as the ration is correct.  Any combination in the 10's of kohm should be ok.

With Cc I mean the capacitor between Vout and Vsense used for the type 3 compensation.

Unfortunately the supply still encounters shutdown/restarts between -35 and -50 degrees celcius. Confirmed on a second PCB. The waveforms below capture the behaviour at the shutdown. As before, restart is immediate. 

blue: 3v3 with 3.3V offset   green: switch node of 3v3 supply. purple: switch node of 5V supply. Yellow shared SS.

I tried to put a probe on a short wire to the compensation pin of the 3v3 supply, but then it occasionally starts to skip a pulse (too much noise pickup?). 

When I remove C391 (Type III => type II compensation, with no change to other components, the supply is stable repeatably doing -50 to 60 to -50 degrees C cycles ( 4 hour cycle time) during at least 24 hours.

Searchable layout (red: top, yellow: mid1 blue: mid2, not shown DGND layer, 3V3 layer, other layers mostly empy or stable signals under power supplies): 1447.6323_04.pdf

I am a bit at a loss here.

What is the best approach to resolve this issue? Going back to a type II compensation? 30kHz is too high for a Type II compensation i presume? Do I need to change the values of C4/R4/C6 (see figure below) when removing Cc (C391)?

fco (kHz)     30 
R4 (kOhm) 8.1      =>  8k1
C4 (F)       3.0E-8   => 33nF
C6 (F)       1.2E-11 => 12pF
Cc (F)       1.6E-10 => 150pf

If you need more information, I will happily cooperate as long as this issue is asap resolved.

I think it might be time we tried to look at the compensation using the pspice model. I can help with this.

I see the compensation components above. What value inductor/DCR are you using? Are the output capacitors still 6x 47uF?

inductor: wurth 7447709150   15uH

Rdc typ: 0.02075 ohm max: 0.026 ohm

rated current: 6.5A saturation current: 8A

SRF: 17Mhz

in/output capacitors as in schematic: so, yes ouput 6x 47uF 10V X7R (Murata GRM32ER71A476KE15 or equivalent)

On the 3v3 plane there is roughly 60-70 uF X7R elsewhere on the board.

Thanks for helping out with pspice, I tried to set it up, but lack the experience and could not get it to work.

One remark: When we see the shutdown/restart, all power supplies are only lightly loaded and the board is idle. I would assume less than 500mA  from the 3v3 supply (only lvc logic and idle io-buffers of a small FPGA).

Based on the schematic above, I'm seeing about 20 degrees phase margin, which is a little low. However, there's virtually no difference with and without Cc...

Based on the simulation, I'm actually having a bit of trouble bringing up the phase margin using this output filter. Still, a 15uH inductor is a little large for this device. Can you try the following:

L = 4.7uH; C = 6x 47uF

R4 = 3.33k, C4 = 22nF, C6 = 100pF, Cc = 1nF. 

Based on the simulation, this gives about 50 degrees phase margin and 22kHz bandwidth. 

20 degrees is not what I would have expected from the SLVA352A app-note. Do you see instability as the cause for the shutdown and restart?

I can try to change those components, but there is a caveat. Until previous Friday, the project was very near to its delivery date. Therefore we had to take the decision to conformal coat the boards (10x) with the components as above (15uH etc), after very little testing time. Now the delivery has been pushed back several weeks, but I would like to work to a solution with minimal change to the components. As we have to solder through the coating and locally reapply the coating.

I find it strange there is no difference according to the model with respect to with and without Cc. It clearly makes a difference in practice. Also the SwitcherPro application calculates the phase margin at 37 degrees for the version without Cc. That's a rather large difference, don't you think?

As I posted previously, that app note is kind of a 1st order approach with a simplified small signal model.  It does not try to predict phase margin at all, but only place the closed loop crossover at a point where there is normally a good amount of phase margin.  I always use pspice myself.  I cannot think of any reason why marginal stability should cause the device to reset.   Marginal stability can cause over voltage to occur during transients and cause the TPS54620 to skip pulses but not reset SS/TR.

As far as the feed forward cap is concerned.  If properly sized it should have quite a bit of effect for a 3.3 V output.  The amount of phase boost available is proportional to Vout / Vref.  I'll try to chat with the IC designer again, but like myself we work for a different group now.

If the COMP pin voltage is railed out positive, it is possible to discharge the SS/TR pin during operation.  CAn you check VSENSE and COMP?

I think I will be able to do so on Wednesday.

Do you mean railed out to 12V (Vin) or 3V (absolute maximum ratings)?

I think teh max clamp voltage on the COMP pin is 1.7 V approximately.  Usually for COMP to clamp at the maximum value, VSENSE must be lower than VREF for some time.  Typically this will occur during an output short circuit. Pulling SS/TR internally down to VSENSE allows the output to recover gracefully.