BQ77910a stacking - BQ shows Short Circuit Charge flag every ~5min when cell balancing is ON

5 min does not seem like a timing from the bq77910A.  The balancing operation should not affect current detection.

In this circuit, the upper IC does not have a way to turn off the current proteciton.  You can set the limits high as you have done with SCC and the trip conditon should never be reached.

Unless you have a large loop in your SENSE connection or floating SENSE pin or ZEDE going high, it sounds like a damaged device.  If ZEDE goes high, delay is set to minimum.  Current is timed based on 30us samples, so minimum will be a single sample above the threshold. If your board experiences some periodic noise pulse which pulls up ZEDE and or the sense pin and it aligns with the current sample, it could trigger. Also ZEDE changes the mode of the part and is disruptive.

The same thing could occur on discharge.  Also be aware the minimum SCD delay is like ZEDE operation for SCD.  To meet the 60us turn off, the part must react to a single sample above the SCD threshold. If you have a system with noise, you may wish to avoid using the minimum SCD setting.

I noticed that Short Circuit Charge flag appears on both '910a when balancing is on. It doesn't matter which type of balancing is set. Flag appears even when there is no current flowing. (only CHGST pin is set high).

Datasheet doesn't say anything. 

Does anyone have problem similar to this?

Thanks for reply WM5295.

I checked voltage on ZEDE pin and is fine. I use EVM to check is this problem only on my board but I have the same situation on EVM. Am I doing something wrong?

When I testing EVM I use resistor kit instead of battery, and put 30V between PACK + and BATT -. CHGST is pulled up to PACK+ and secured by 2 diodes in series to GND (voltage on CHGST is about 1,4V).

Good parts don't do that.  Polling the status is disruptive and may induce a SCC, but some fault must have turned off your FET to begin with.  I'd replace the part.

This sounds very similar to a problem I've been having.  However, in my design, the short circuit flag is latched 7.5 minutes after the CHGST pin is set high.  Coincedentally, 7.5 minutes is also the cell balance update interval.  I have probed the balancing circuit for the highest voltage cell in my test setup, and verified that the cell balancing begins at almost the same instant the short circuit charge flag goes high.

I have tried several experiments with and without the USB-TO-GPIO adaptor connected, as I wanted to make sure that pulling on the ZEDE pin was not the culprit.

I have tried several different BQ77910A parts, including one that is approximately a year old, just to make sure the problem wasn't unique to a recent batch of parts.  All have exhibited the same behavior.

I have a BQ34Z100 as part of my battery management circuit as well.  It is possible that they are somehow interacting and causing a fault.  But if that's the case, I can't identify what the interaction would be in my design.

If anyone has any more input regarding this problem, I would be very grateful to hear it.

If you are polling status in normal operation you will likely eventually induce a fault with or without balance in any '910A.  In order to enable the interface to read the status, ZEDE must be set so the current comparators are set to respond to any sample above the threshold.  The interface signals are swinging 3.3V and are a potential noise source.  When balancing is running, the internal balance FET discharges the input filter capacitors at each turn on causing a current surge which is another noise source.

You have encountered some systemic problem which would not seem to be the particular part since you have tried multiple parts.  Certainly we don't expect the part to behave as you experience in normal operation.

Without the USB-TO-GPIO connected, inspect ZEDE for crosstalk from other signals.  In general the ZEDE line should have a heavier pull down than the USB-TO-GPIO can drive.

The bq34z100 should not particularly influence the '910A.  Its operation will have switching of the communication signals and the battery voltage which are noise sources.

It may be beneficial to correlate the DSG fall to some other signal swing occuring a few to 100's of us before the DSG drop. Then look at signals which may be crosstalk victims.  It would be easier if the device debug interface did not have the potential to induce errors, but that is the way the part works.