LM3481 SEPIC shuts down on Vsupply surge

Hello Luciano,

It'll be of great help to our Applications team if you can post your schematics, PCB layout, Load current conditions and scopes of some of the waveforms you've taken that way we can review and understand  your problem much better.  Thank you!

Best Regards,

-Juan 

Hello Juan,

here you'll find the schematic of the power supply:

0247.schematic.pdf

here's the PCB layout; it's a double layer with components on both sides:

top layer: 2605.Top Layer.pdf

bottom layer: 5618.Bottom Layer.pdf

here are the scope screenshots: 8371.screens.pdf

Sorry but I haven't found a way to paste readable images.

Many thanks for any indication you could provide,

Kind regards,

Luciano

Hello Luciano,

Juan and I went through your collateral and have some comments. 

1) Would you please tell us what loads you are looking at driving? Certain BOM components might need to be recalculated from what they are on the AN-2094

2) In your screenshot, one of the plots is that of pin 10 and is labelled Vcc. This cannot be right. Pin 10 is Vin and Pin 9 is Vcc. Also Vcc has an abs max of 6V. Therefore if indeed it was a Vcc plot, then there is something wrong and the part would most likely malfunction. Would you be able to take the plot of the voltage at pin 9 (Vcc)?

3) Your SEPIC cap value is set to 1.5uF. I believe this is quite small. I would suggest that you use atleast 4.7uF and make sure that the caps can handle the right RMS current. I would suggest the same for your Vcc cap. About 1uF should be used.

4) We believe your problem could be related to the layout. For the SMPS topologies, the ground return path for the high frequency currents needs to be defined well and the loop comprising the path should be as tight as possible and on the same layer. Here the loop formed by the FET, Csepic, Diode, Cout, and Rsns should be kept very tight and small. On your board this is not continuous and travels through vias. Having vias on switching current paths is not so good because it adds more stray parasitics in to the path. Please refer to the AN-2094 layout for reference.

5) Your FB node is going through a via also. The FB node should be as small as possible and should be very close to the pin. The FB ground should also be as close as possible to AGND. The same applies to COMP node. Your COMP node is passes through a via and the R-C components are right next to the DR trace. This trace carries switching current and could couple noise on to it. If any of these sensitive nodes have noise coupled on to them, the system could behave erratically. From your plots, it is difficult to say if Comp is falling because of the part reset or otherwise. If Vout drops, COMP usually rises which translates to higher duty cycle. 

6) The Csns cap should be kept as close as possible to the ISNS pin on the layout. This helps in filtering any noise on the current sense signal.

7) As mentioned before, the high frequency caps used at the output and the diode are a part of the high frequency current path. These should be kept on the same layer as the FET, Rsns and SEPIC caps.

8) You have used relief connects at many places. They add more parasitics in the path and they should all be replaced by direct plane connects.

When there are no apparent errors in the BOM and if the circuit is still not working properly, then it usually means that the layout needs to be optimized. I have attached a presentation here which goes over how to layout the circuit to avoid EMI. 

One more thing you could do is use the EVM mentioned in AN-2094 and see if you could use it for your design purpose. I hope this helps.

Regards,
Akshay 

Hello Juan,

thank you for your comments; here my answers to your remarks:

1) sorry, I forgot to mention it. The circuit is oversized for a maximum current of 1.5A, but in reality the output current is never higher than 500÷600mA

2) The plot is referred to Vin (PIN 10); I didn't save the Vcc (PIN 9) screenshot but I checked it and nothing strange appeared.

3) Tried to increase it to 3uF, no effect. Already increased the cap on Vcc to 10uF (ceamic) with no effect.

4) I too have though to this; I well know thas passing signals through vias is not correct but the distances are very small and cannot do otherwise. The components, capacitors in particular, directly connected to the IC are as near as possible to its pins and, if on the opposite side, diretly under the IC. Anyway, I cannot see on the scope anything strange on the IC pins, which I would aspect in case of coupling of any nature.

5-6-7-8) you're obviously right and I investigate it FB signal as first thing; no spikes, noise, variation or strange things on it. The same on the other pins except COMP; I have already added ceramic capacitors on each DC pin with no effect. Also shorted the current feedback signal to GND directly on pin 1; the controller still works but again stops on surge. It doesn't stop only when R314 is disconnected or FB is shorted (without the MOS), but the same variation (maybe just smaller) on compensation pin appears. I don't understand why, without any FB variation, the COMP pin signal drops and stays low for so long.I cannot even understand whi the MOS command disappears and stays off  fo so long after the surge impulse.

What worries me is that the LM3481 SEPIC evaluation board (with a varistor on its supply, a 200mA load and a smaller surge amplitude) has the very same behaviour, having a much better layout design than mine. My fear is that this could be a topology or component related problem, and I have to change the full power supply design on my application. 

Again thank you for your attention and kind regards,

Luciano

Hello Luciano,

Thank you for informing us that you have tried the eval board also in place of your own board. If both the boards are exhibiting the same behavior, then it might not be completely layout related. Although, I do stand by what I said before about the layout. Also, when you said this behavior happens when you use the SEPIC eval board, does it happen in the same exact way, where only the COMP node dips and Vout collapses and all other nodes seem to be alright and within boundaries?

Based on your design inputs, I tweaked some BOM components. I would encourage you to try those. I am using your 1.5A as the worst case load. The new values are as follows:

L = 8.2uH Part no. = MSD1278-682. I have reduced the inductance value and sized it to 20% ripple current at 1.5A load switching at 500KHz.

Rsns = 25mohms
Csepic = 2x4.7uF
Vcc = 2.2uF
Rcomp = 6.8k ohms
Ccomp = 0.047uF

It is not clear to me whether the abnormalities on COMP are a cause of DR turning off or a result of DR turning off. Logically when Vout drops, COMP starts increasing. This problem should really not be a topology based. Actually, from your screenshots, I see that the input rises fast only to about 35 to 40V. This should actually be in range. If the input is in range, I am not sure why the Vout collapses. How fast is the surge hitting? 

Let me know what the results are like with these updated components.

Regards,
Akshay 

Hello Akshay,

the surge applied is compliant with the standard EN6100-4-5; the voltage level specified by the standard  is 2kV 1.2/50 micoros.

I used a EM TEST UCS 500 generator; I can set the surge voltage level as I wish and I saw that the LM3481 stops at around just 500V.

I tried the modification you suggested, but with no results.

I used L=10uH (what I had available) 

Csepic= 2x4.7uF

Vcc=3.3uF, then 4.7 and 10uF ceramic

Rsins=25mohms (parallel of two 50mohm)

Rcomp=68k

Ccomp=0.047uF and then also other values.

I think anyway that it is not a problem related to the inductor, the Csepic or the regulating loop. As I told you, I removed the MOS, so to have its PWM gate signal alway at full rate. I also removed the Csepic.

I made this just to see if there was a stability or regulation problem. In this configuration obviously the inductor is not working, there is not Vout and no regulation loop.

No way; the PWM output still stops on surge and the COMP signal still decrease as in the screenshot, with no particular difference.The regulator keeps on working only when FB is connected to ground (but no spikes on it when not grounded).

So I think it is not a problem related to the values of the inductor, Rsens, L, Csepic or other components but it may be directly related to the topology or the chip itself.

In the past I used many of TI regulator (LM2574, LM2575, LM5010, LM5005 etc.), with similar surge protection design and with no problem at all; this is the first time I see the regulator stop itself.

The real problem it's not the fact that the regulator stops for a monent, but that it restarts only after a long time and this cause a major drop on the output voltage.

Hope this will be of some help,

again many thanks and regards,

Luciano

Hello Luciano,

We are going to have to investigate this. I am going to involve my team in this and let you know once we have some answer.

Regards,
Akshay 

Hello Akshay,

any news about my problem?

I and my colleagues are going to define some new similar project and SEPIC regulators made with LM3481 would be the best solution as power supply, but we need to be sure there is a way to make it work correctly in compliance with the EMC requirements and the surge EN standard

Thank you and regards,

Luciano

Hello everybody,

we're studying a new device and we're still in need of a SEPIC converter which can withstand the surge test of the EN standards without stopping itself.

For our old device, object of the previous posts, since it was already in a pre-production level, the problem was "solved" adding a very large quantity of capacitors on the 5VDC output to supply the load until the controller restarts, but this is not the right approach.

It's passed one year; have you analyzed the problem, as by your last post?

In the case, can you suggest an alternative to the LM3481 with similar specs but not subject to this kind of troubles?

Thank you for your interest and regards,

Luciano