This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS92075 gate drive capability

Other Parts Discussed in Thread: TPS92075

Hi

Unfortunately I was not able to find any parameters for gate driver capability of the TPS92075 on the pin Gate.

Could anyone help with definition requirements for the power FET which is used with TPS92075?

What gate charge could be driven by TPS92075?

  • i)From the gate drive section of the datasheet: Gate drive resistance = 8Ohms max.

    ii)FYI:  Peak current capability would be based on Vcc/Gate drive resistance. If Vcc = ~12V / ~8Ohm max = ~1.5Amps peak. (In case you are used to gate drivers being quoted this way)

    iii)Max charge depends on power dissipation of the package and frequency of operation. If you assume ~100kHz. Then from Pgate = Vgate * Qgate * f we can find the max gate charge.

    iv) For the SOIC THETAjA = 112'C/W . So if we choose a conservative 25 degree C rise we can disipate 223mW.

    v) We assume a Vcc of ~12V then:  Qgate= Pgate/(Vgate * f):  0.223/(12 * 100k) = 185nC

    vi) One FET used on a TPS92075 EVM was the FDD6N25. It has a Qg of 6nC max and this FET would handle most LED drive applicaitons up to ~25W easily.  So we can see from this that unless you are doing something extremely high in power (>300W maybe), or wish to run at a very high frequency, you can probably use pretty much what ever FET you wish.

    Thanks for posting your interesting question.

  • Hi, Tim,

    Thanks for your detailed answer.   I'll take it for consideration/

    About high frequency  solution I guess it will be omitted by TPS92075 architecture and minimum off-time value.

    BTW could you suggest where I could find the  minimal value for toff which could be implemented for TPS92075?

    In the datasheet I found only  Maximum off-time - 280us