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tps56121 review

syed hamad
Expert 1120 points
Other Parts Discussed in Thread: ADS4149, ADS4249, TPS56121

Hi guys

I have inserted the Schematics

3716.7534.SCHEMATIC1 _ 04_ FPGA Power,ADC.PDF

5873.0172.SCHEMATIC1 _ 04_ FPGA Power,ADC.PDF

below is the query from one the customer,

As shown in the schematics, we are deriving following digital voltage rails from 5 V DC input: 

 

a. 3.3 V, up to 5 A Max

b. 2.5 V, up to 5 A Max

c. 1.8 V, up to 5 A Max

d. 1.1 V, up to 4 A Max

e. 1.0 V, up to 5 A Max

 

Apart from the above digital supply rails, we are also using few LDOs to derive AVDD and DVDD for HS ADCs (ADS4249 and ADS4149). 

 

Attached schematics correspond to second revision. 

 

In the first revision, which is being tested now, following issues have been observed and we would like to make sure that these issues are resolved totally in the second revision: 

 

1. During the initial power ON time, current (monitor on the 5 V DC supply, being fed from Agilent or Aplab supplies) is shooting up and is settling down to lower and proper value after few minutes. 

2. During Platform flash (of Xilinx V6 FPGA) loading, current is fluctuating by at least 1 Amp. After the programming is done, current settle downs to proper value.  

3. 1.1 V DC output, being generated through tps56121 switching regulator is not coming properly. Hence, currently, we are feeding this voltage directly from an external power supply.  

4.  We have seen failure of the LDO regulators, i.e TPS7A8001DRB (at least 2-3 devices were replaced in 4 boards) used for powering HS ADC1, HS ADC2.  

pls addres the query,

regards,

syed hamad.

  • 0
    TI__Expert 4350 points

    Syed,

    Thank you for your interest in TI parts. The two schematics you attached appear to be the same page, and I can't find the TPS56121. Can you please verify?

    MC.

  • 0 in reply to Martin Cardella
    Expert 1120 points

    Hi Martin,

    Thanks for your response on my post,

    Below is the schematic for Tps56121,this is urgent requirement can you pls verify and let me know your feedback,

    waiting for your valuable feedback.

    1258.SCHEMATIC1 _ 03_ Power Section.pdf

     

    regards,

    syed hamad.

  • 0 in reply to syed hamad
    TI__Expert 4350 points

    Hi Syed,

    I don't see too many issues with the schematic that are obvious problems. I will say that the 56121 is a 15A device and the schematic shows an OCP setting of 20A, but your stated max load current is only 4A. This is not necessarily an issue, but it implies that the switcher can source as much as 20A into your load during fault conditions.

    The other implication of this setup is that the peak-peak ripple current in the choke is 3.9A. This would be appropriate for a 20A OCP, but with a max expected load of 4A, this ripple is 97.5% of full load. Normally the recommended ripple/(full load) is 20% to 30%.

    I did not check the loop compensation. How did you calculate the 5 compensation values?

    Can I ask you to post some waveforms that detail what the issue is? Please include Vout, SW node, SS, and Vin as a start. I would need to see these at different time bases that show a few switching cycles, and then maybe zoomed out to see the issues on Vout.

    MC.

  • 0 in reply to Martin Cardella
    Expert 1120 points

    Hi martin,

    Thanks a lot for your reponce on my post, by this i have some idea on resolving issues,

    yes, i will check waveforms and post it so that it gives you more clearity,

     

    regards,

    syed hamad