We are using the LM5069-2 and I was hoping to clear up my understanding of its operation. The goal of our design is to satisfy requirements of UL864. One of the requirements is to sustain a load of 10 amps for a duration of 17mS. The current sense resistor has been set to 0.008 ohms, setting the current limit anywhere between 6 and 7.8 amps. This calculation assumes a 1% tolerance on the current sense resistor and takes into account the threshold voltage range specified in your specification sheet. The capacitor Ct has been set to 1uF, allowing for a timeout period of 47mS (equation 3 on page 17 of the data sheet).
The section of UL864 that concerns us for regulated circuits requires testing with a resistive load only. To make this discussion simple, let us say that we will implement current limit only and the UVLO and OVLO pins will always be biased to keep the device on. Also, insertion time is of no concern for us in this test. I would like to discuss the in-rush limiting time as we are loading the circuit beyond the current limit. With this in mind I have the following questions:
1) You discuss modulation that occurs when exceeding the current limit. Does this “modulation” mean that you are turning the FET on and off as needed or would you try to maintain FET operation in the linear region?
2) Is there a minimum capacitance that needs to be provided on our printed circuit board to allow for testing with a purely resistive load?
Could you describe what should occur as we increase load current between 5 and ten amps. Do you have any recommendations that would help us sustain a load beyond the current limit for a short duration (at once per minute).
Thanks.
