TPS54618 EN disable timing

That delay time is not specified.  I doubt that there is characterization data for it.  I may be able to get an estimated delay time.

As you wrote, I couldn't find that delay time.

Is it possible to get this delay from the chip design team, or is testing the only way to get this value?

I'd appreciate any information on that signal path timing.

The time seems somewhat long...I am going to check it again.

So, from EN enable/disable strobe until the internal FETs gates enable/disable strobe it taked 100us for the 54618 and 5us for TPS54218318/418.

Is it a theoretical number? An empirical number? Is it a guaranteed number?

Do you know if these numbers are typical to other DC/DC (not necessarily TI)?

Thank you for your effort.

Those numbers are from one of the design managers, who actually did the design for the TPS54418, which was the first device from that family.   I'm sure he looked at the design schematics and estimated the approximate time based on a visual inspection of the logic blocks.  He checked some release notes to verify that the longer delay time for TPS54618 was intentional.  So the 100 usec is just an estimate.

 There is quite a bit of varaibility in EN operation among devices.  I know that some have internal initialization and calibration routines that occur before switching.  theres enable / dissable within one or two switching cycles.

The TPS54618 designer is no longer available to make additional comments. 

Thank you John Tucker for your help!

It is much appreciated.