TPS5450 blows up

The TPS5450 does have thermal protection.  Usually if you are getting high side FET shrt to ground, it is due to EOS (overvoltage).  Do you hot plug or switch on your power? is there any OVP on the input?

Hi John.

Yes,in my board there is OVP on VIN ( a transil SM6T36CA).

During production test I switch the power or also hot plug it; you consider that the same power supply is connected to a second TPS5450 (in the same board) that generate a 12V, but on this I haven't no kind of problem.

Hi John,

any news about my problem?

regards

Luca

I would suggest that you monitor the TPS5450 input voltage during your power cycling tests.  See if you can capture any input transients that exceed the absolute maximum for the device.  I think it is reasonable that one device may be more susceptible due to layout factors.  If you post your schematic and layout I can take a look at them.  Also, you can contact your local FAE.  He can arrange for failure analysis on one of your bad devices.

I have checked the input voltage but I can't see any transient input more than 30V.

I append the pdf with schematic and pcb.

Where any of the ICs damaged when you did the additional testing while monitoring Vin?  You could always submit one of the failed devices for failure analysis.

i looked at your schematic and layout.  the output filter looks rather complex with a mix of capacitor types. That is not necessarily a problem, but it may be somewhat difficult to compensate the closed loop.  Have you measured the loop stability?  Are there any start up anomalies on Vout or PH? 

The layout looks a little iffy.  It is somewhat more spread out than I would recommend.  I usually like to get at least one of the input caps directly across VIN to GND as close to the IC as possible.  It is hard to follow all the details in the layout graphic you sent.