TPS54478 VIN overshoot

I'm not sure about your question.  Do you have the TPS54478 converter operating with 5 V in and 1.2 V out, then very quickly short the output voltage or are you pulling PH to ground?  Are you just observing local VIN overshoot during that time?  5.5V would not exceed the abs max for TPS54478.  Let us know if you can clarify your concern.

Hi

Thank you for you reply.

Please let me explain more detail.

As you explained, it was observed VIN overshoot during quickly short output by FET switch.

Of course we checked VIN and PH pin voltage.The both pin voltage were not exceed abs max.

But some samples has been shorted between VIN to PH because of EOS/ESD.

We already investigated general cause but we did not found any cause.

Finally, we checked two waveform what I posted before. We concern why VIN waveform is different each other.

This is just hypothesis. Is VIN behavior different when output is shorted if each sample has different current limit threshold?

Please let me know if you have any question.

Regards,

I do not know of any direct mechanism between shorting the output, and creating an EOS condition. TPS54478 has a current limit function.You should be sure to check the PH and BOOT spikes at the time of the short circuit too, in addition to just at steady-state. For these measurements, it's also that they're measured directly at the device pin, and with a tiny ground loop. 

Are those plots above the exact moment when the short is applied, and the part hard-fails? or does this happen during a repetitive cycling of an output short? Are you expecting to input crash after the short circuit?

If I understand correctly, they have experienced some device failures with VIN to PH shorted due to EOS.  This is a fairly common failure mechanism that we have seen across a lot of different products where over voltage conditions can damage the high side FET.  What I think they are trying to do is simulate this in a controlled environment.  The real EOS failures can occur at unpredictable times so that it is not possible to observe the input voltage condition at the time of the failure.  So they are intentionally shorting Vout to GND and measuring the Vin voltage to look for over voltage conditions.  they are not seeing any over voltage above 5.5 V, but are concerned that the VIn waveforms are "different".

I suppose it would be best if they can supply additional waveforms including PH voltage, COMP voltage and inductor current.  They would need to provide both the same 20 usec/div and maybe a zoomed in time scale of 2 usec/div to allow us to resolve individual switching cycles.  I think then we can explain any differences.

Hi 

Thank you for quickly reply.

We have only waveform of PH pin now. Please see below. (This is not failure sample's result.)

We are going to ask customer to take waveform of COMP pin and BOOT pin as well.

regards,

We would need to see the PH pin duty cycle variation in the time scales indicated in my prvious post to see what is happening.

Hi 

Thank you for your reply.

I got a new waveform from our customer.

Please see attached file.

Please let me know if you have any question.

5621.TPS54478 Waveform　20131219.pdf

Regards,

K

Hi

Please give us the advice for previous post.

regards,

K

The waveforms in your later post do not resemble the waveforms from the original post.  I suspect it is an artifact of your input supply, the cabling and the input capacitance (or lack thereof).  Can you tell us about the input supply, how it is attached and how much input capacitance is on the board?

Hi

Sorry for late.

I confirmed to customer about your questions. The answer is below.

- Input supply : DC/DC converter which means switching regulator.

- cable : There is not any cable. TPS54478 and input supply are connected by short pattern on same board.

- input capacitor : 10uF

regards,

K 

What is the output capacitor of the upstream dc/dc converter?  How wide and long is the connecting trace?

Hi

The capacitor which is for upstream of DCDC converter is ceramic capacitor (10uF x 7).

Please refer below about trace size.

regards,

K

This is additional information.

The customer exchanged from failure sample to another sample on same board.

Then they tested again.

But this failure did not happen.　The rate of this failure is 13/540.

regards,

K

Then I would suggest that you submit 2 or 3 failed parts for failure analysis.

Hi

Thank you for your reply.

 We already requested you(TI) to analyze failure sample before .The result was EOS/ESD.

 The metal line between Vin-PH was damaged.(There are several point include FET.)

I have two question for this issue.

 1. As your comment,the waveform(poseted Dec 10 2013 19:29 PM) is not abnormal waveform such as damage to device.(like EOS/ESD)    

  Is that correct?

 2.In spite of analyzed and confirmed the waveform the root cause was not found.

  So we concerned this issue related manufacturing variation (or process variation or some parameter)

  Is it possible cause of this issue?

Please let me know if you have any question.

regards,

K

The waveforms from 10 Dec show VIN to be below the abs max voltage.  The waveform has an unusual shape, but I do not see any damaging voltage levels.

I suppose it is possible that there are some variation in due to process, but I think that is somewhat unlikely.  I would think there is a much greater chance the variation is in the operating condition.  You stated in a previous post that the VIn traces are 2 mm wide.  That is rather narrow.  When I design PCB, I always use copper fill areas for the main power traces of Vin, Vout, PH and GND.  The GND may also include plane layers.  You might also consider moving some of the  7 x 10 uF over to the other side of the coil where there is only 1 x 10 uF.

Hi John

Thank you for reply.

As you commented below,

>I suppose it is possible that there are some variation in due to process, but I think that is somewhat unlikely. 

>I would think there is a much greater chance the variation is in the operating condition.

What kind of variation that you supposed is there?

That is what I and customer concern.

Regards,

Koji

Hi John

I understand my question above is difficult to answer.

But I need some information to consider what is cause (include possibility) .

The customer require us to talk about this issue as soon as.

Regards,

Koji

Hi John

The EOS condition is 

 - When the output shorted directly by FET switch.

 - When it is Immediately after the high side FET on.

regards,

Koji