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ddr issue with twl6032

jags vg
Intellectual 865 points
Other Parts Discussed in Thread: TWL6032, TWL6030

Hi All,

We have our custom board based on pandaboard-es with omap4460 processor, but we are using twl6032 pmic instead of twl6030.

We are busy in bringing up our board, and initially we are trying it to boot it through usb.

we are using usbboot utility for usb booting.

We are getting some issues in ddr initialization. ddr is getting voltage from smps3 by pmic twl6032.

in our reference board(pandaboard es), ddr is getting voltage from smps6 which have default voltage.(1.29 V).

there is some changes in twl6032 and twl6030. inside twl6030, VCOREx_CFG_FORCE registers are used to change the voltges. but in twl6032, only 3 registers are available for CFG_FORCE.

SMPS1_CFG_FORCE

SMPS2_CFG_FORCE

SMPS5_CFG_FORCE

and our ddr is getting voltages from SMPS3.

I have tried to set voltage for ddr through SMPS3_CFG_VOLTAGE register, but i am not successful.

I think we can set voltages only through SMPSx_CFG_FORCE registers, and they are not available for SMPS3,4 and 5.

Que:

We are taking voltage for ddr from smps3, is it ok? or do we need to take voltage for ddr from smps1,2 or 5?

For SMPS3_CFG_VOLTAGE register:

bit 7 is WR_S, 

Warm reset sensitivity
0: Reload the default VSEL [5:0] value when a warm reset occurs
1: Keep the voltage configuration settings, same VSEL [5:0] value just
before the warm reset event

Can anyone explain me the meaning of above description?

--------------------------------------------------------------------------------------------------------

Thanks,

Jags vg

  • 0
    Intellectual 865 points

    Hi All,

    The issue is in below function.

    void lock_core_dpll_shadow(void)
    {
    dpll_param *dpll_param_p = &core_dpll_param_ddr400mhz;
    u32 temp;
    temp = readl(CM_MEMIF_CLKSTCTRL);
    temp &= (~3);
    temp |= 2;
    writel(temp, CM_MEMIF_CLKSTCTRL);

    while(readl(CM_MEMIF_EMIF_1_CLKCTRL) & 0x30000)
    ;

    while(readl(CM_MEMIF_EMIF_2_CLKCTRL) & 0x30000)
    ;

    /* Lock the core dpll using freq update method */
    /*(CM_CLKMODE_DPLL_CORE) */
    writel(0x0A, 0x4A004120);

    /* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1,
    * DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1
    */
    writel(0x70D | (dpll_param_p->m2 << 11), 0x4A004260);

    /* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */
    while((readl(0x4A004260) & 0x1) == 0x1)
    ;

    /* Wait for DPLL to Lock : CM_IDLEST_DPLL_CORE */
    wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);

    //lock_core_dpll();

    while(readl(CM_MEMIF_EMIF_1_CLKCTRL) & 0x30000)
    ;

    while(readl(CM_MEMIF_EMIF_2_CLKCTRL) & 0x30000)
    ;

    writel(temp|3, CM_MEMIF_CLKSTCTRL);
    }

    --------------------------------------------------------------------

    writel(0x70D | (dpll_param_p->m2 << 11), 0x4A004260);

    By above line, 

    it is trying to write in  CM_SHADOW_FREQ_CONFIG1 register. /* omap4460 TRM page no: 850 */

    Inside this register, It is trying to enables the DPLL in lock mode.


    and here it is not getting success, and after that my board is resetting.

    Please give the answer if anyone can.

     

     

    --------------------------------------------------------------------------------------------------------------------------------

    Thanks,

    Jags vg

  • 0
    TI__Expert 6090 points

    CFG_FORCE registers are only for the SMSP which has DVFS functionality other wise you should be able to change the voltage using SMSP_CGF_voltage register.

    you cshould check if the can read and registers and the values are changing.  As long as DDR does not exceed the max load capability of SMPS3 it shoulf be ok.

    The above description is about WR_S bit , if ( SMPS or LDO ) is a part of warm reset sequnce the votage will only come to default value after executing the warm reset sequence if and on if WR_S bit is set. If this bit is not set reource will keeep its state before warm reset sequnce. Each resource has its accociated bits.