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TPS40304 Switching Frequency

Bill Drumheller
Prodigy 135 points
Other Parts Discussed in Thread: TPS40304

Hello,

I am using a TPS40304 Buck controller in a POL circuit that converts 5VDC to 1VDC at 16A.  I currently have three of these circuits on a board powering 3 different loads and 2 of the 3 seem to be working fine, i.e. low ripple voltage and correct output voltage of 1.0VDC.  However, one of the circuits (which is identical other than tweaks to layout) has the correct DC voltage but much higher ripple than the other 2.  When probing the low side drive and SW pin of the IC, I noticed that this IC is operating at half of the specified 600kHz (300kHz).  When checking the other 2, they are indeed operating at 600kHz.

I have checked the markings on the ICs to be sure they are the same part and they are.  Any ideas what could cause a shift in the switching frequency since I thought this was a fixed frequency PWM?  Could it be caused by noise in the feedback, insufficient soldering of the underside ground pin, etc.?  I am using voltage mode control so it would seem that pulse skipping due to minimum duty cycle would be out of the question.  The block diagram in the datasheet doesn't give me enough info to determine what might cause a change in switching frequency either.

Thanks,

Bill

  • 0
    TI__Expert 4350 points

    Bill,

    Thank you for your interest in TI parts. It is possible that the loop locks in to Fsw/2 for a few reasons. Layout and noise can definitely affect this phenomenon, as well as loop compensation design. If the layout is such that the actual output voltage ripple is high (or higher than the other switchers), this can result in the ripple being reproduced at the output of the error amp, which is the COMP pin. The amount of amplification will depend on the loop compensation since that sets the complex gain of the error amp. So if the EA gain at Fsw/2 is relatively high, then output ripple gets amplified and shows up at COMP. If the ripple at COMP is high enough, it can cause the loop to lock in to Fsw/2.

    The device clock ramp is likely still 600kHz, but that ramp is compared to the COMP voltage and the output of the comparator is the raw high-side gate drive (before additional logic and prop delays). If COMP has ripple at Fsw/2 of sufficient amplitude such that the peaks of the COMP ripple intersect the clock ramp but the valleys do not, then the result will be an effective Fsw/2. Exacerbating this is that the inductor current ripple and output voltage ripple will be higher at Fsw/2, which tends to "lock" the loop into Fsw/2.

    It is also possible that the actual output voltage ripple be well behaved, but the feedback signal or even the COMP signal get corrupted by switching noise. If the result is relatively large ripple at the COMP pin, the result can be the same, that the loop gets locked into Fsw/2.

    Have a look at the COMP pin voltage to see if there is much larger ripple (as compared to your other identical switchers). As a quick test, you can add a large value cap (try 1uF ceramic) from COMP to FB to greatly reduce the bandwidth of the EA (and reduce its gain at Fsw/2). Likely this will result in a return to 600kHz, but you will need to investigate further which part of the physical design needs to be improved.

    MC.