LM3478 switching noise

Hi,

Question 1.  Noise.  This type of high frequency noise is usually due to layout.  On a boost converter the important loop is between the the FET drain -> diode -> output cap -> and the FET source.  Try to make this loop as tight as possible.  Look at adding some x5r or x7r 0.1 to 1uF ceramic capacitors to the output as close to the source of the fet and the diode as possible.

Question 2.  There can be variation in the current limit due to mosfet on resistance and other factors.  If the on resistance of the FET is lower than expeced this would lead to a high current limit.  Try adjusting the limit down.

Regards,

Marc

Hi Marc,

Thank you for your quick answer!

Qusestion 1: Noise

As you can see on following pictures I doubled input and output electrolytic capacitors and added stacked ceramic X7R capacitors (100nF + 2.2µF):

With these additional capacitors switching noise is lower:

CH1 Vout, CH2 Vin, Output current 1A:

CH1 Vgs, CH2 Vds, Output current 1A:

If necessary have a look at PCB layout:

I assume critical path is right, isn’t it?

How to improve noise immunity?

Qusestion 2: current limit

I doubled Rsense value (from 12mhom to 24mhom). Using 12mhom, duty cycle starts decrease from 4.5A. With 24mhom, duty cycle starts decrease from 2.2A

So it is better, but I don’t know why exactly as Rdson of these 2 MOSFET (CSD17308Q3: webench; PSMN9R5-30YLC: used) are almost the same.

Before measuring I thought that in case current limit was reached, the output voltage would drop immediately to 0V. But actually the duty cycle is gradually reduced.

Could you confirm?

Moreover I suppose changing Rsense must involve compensation slope adjustments. Is-that right?

Best regards

=Same message pictures uploaded correctly=

Hi Marc,

Thank you for your quick answer!

Qusestion 1: Noise

As you can see on following pictures I doubled input and output electrolytic capacitors and added stacked ceramic X7R capacitors (100nF + 2.2µF):

With these additional capacitors switching noise is lower:

CH1 Vout, CH2 Vin, Output current 1A:

CH1 Vgs, CH2 Vds, Output current 1A:

If necessary have a look at PCB layout:

I assume critical path is right, isn’t it?

How to improve noise immunity?

Qusestion 2: current limit

I doubled Rsense value (from 12mhom to 24mhom). Using 12mhom, duty cycle starts decrease from 4.5A. With 24mhom, duty cycle starts decrease from 2.2A

So it is better, but I don’t know why exactly as Rdson of these 2 MOSFET (CSD17308Q3: webench; PSMN9R5-30YLC: used) are almost the same.

7345.MOSFET_CSD17308Q3.pdf

8688.MOSFET_PSMN9R5-30YLC.pdf

Before measuring I thought that in case current limit was reached, the output voltage would drop immediately to 0V. But actually the duty cycle is gradually reduced.

Could you confirm?

Moreover I suppose changing Rsense must involve compensation slope adjustments. Is-that right?

Best regards

Critical loop is high light above.  You want to place the ceramics as close to the bottom of the sense resistor as possible to filter high frequency noise.