I am using CDCE62005 and CDCE62002 in my design. (http://www.ti.com/lit/ds/scas862d/scas862d.pdf)
Page 70 starts a discussion of thermal management. Page 71 shows the recommended internal via configuration between the chip side and the backside thermal surface.One of the internal layers is ground in the diagram shown.
Does TI recommend thermal relief between the internal ground layers and the ground vias?
For clarification, does TI recommend thermal relief between the backside exposed thermal pad and the ground vias as shown in Figure 41?
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