Dear Sir,
I am writing this email regarding the application of SVS IC TPS3613-01.
(Adjustable battery-backup supervisor for RAM retention).
We have designed our circuit with reference to data sheet SLVS340D – Dec 2000-Revised July 2008.
In our circuit, VDD = 3.3V, VSENSE is derived from 5V, VBAT = 3V
Problem scenario:
During power off sequence, Vout signal shifts from VDD to VBAT as desired when VSENSE voltage is crossed.
While VDD is falling, the Vout again shifts back to VDD as the VDD crosses VSENSE.
This results in data corruption as VOUT falls down with VDD.
Relevant circuit diagram of my circuit is attached. And I have also attached DSO waveforms of OK and not OK instances.
We think this might be malfunctioning of IC and we request your help to resolve this issue.
Matter is very urgent because this problem of RAM corruption is reported from customers.
NOT OK Waveform
OK Waveform
Also please let me know contact details so I can get in touch with any FAEs.
Regards,
Sushant
