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TPS40131 Transient Response Issues

John Muren
Prodigy 135 points
Other Parts Discussed in Thread: TPS40131

Hi,

     I've recently designed a regulator using the TPS40131 dual phase buck converter.  Input is nominally 24V, output is set just above 5V, with a peak output current of 40A+, running at 500KHz.  The circuit is capable of handling the 40A as long as the rise time of the current transient is slow enough.  If a fast load transient occurs, the power supply behaves as if it has experienced a short circuit event (both high and low side FETs shut off, soft start capacitor discharges and goes through seven charge-up cycles as if in hiccup mode), even if the actual current level was low to moderate.  These fast current transients have potentially sharp rising edges (>50A/us).  This design also has some tight ripple and Voltage transient constraints, requiring lots of output capacitance.  Current design is using two 2.2uH, 2.25mOhm, 35A inductors (one per phase) with a total output capacitance of around 22,700uF (15 x 1500 Al El low ESR caps, 22 10uF ceramic caps).  To complicate the design, there is a need to isolate the output via pass-FETs to allow for quick disconnect from the regulator.  These FETs have a very low RDSon (about 2mOHM, qty 4), and when off, force the regulator Enable off as well.  Remote sensing is used to the node on the output of the pass FETs. 

     A couple of notes about the inductor current sense:  I'm using the recommended method ("lossless" inductor DCR sense), but needed to add a parallel resistor to the capacitor that goes across the CSx/CSRTx pins.  Per the datasheet, I adjusted the resistor values so that the R/C time constant should match the L/DCR time constant and maintain Vc, the voltage across the CS/CSRT pins, under 60mV under maximum normal inductor currents.  It doesn't appear that Vc is getting high enough to generate an over-current when the event happens (I even increased the voltage at the ILIM pin to 350mV to avoid an over-current trip, but it didn't help).

     I've adjusted the compensation network (using Type III) to the best of my ability using both the datasheet recommendations and the results of the MathCad spreadsheet for looking at the Bode diagrams for stability.  This has helped overall, but has not fixed the issue.

Any ideas what I should do next?

Thanks,

John

  • 0
    TI__Expert 4350 points

    John,

    Thank you for your interest in TI parts. Can you either detail or post pictures of the schematic and layout? How is the ILIM voltage being generated? Do you have a filter cap from ILIM to GND? Can you post snapshots if the ILIM pin and the CS and CSRTN pins during a load transient?

    Regards,

    MC.

  • 0 in reply to Martin Cardella
    Prodigy 135 points

    Martin,

         ILIM is generated from a voltage divider off of VREF and voltage is set for 255mV (10K//5.76K);  there is a 0.1uF capacitor in parallel with the lower resistor.  Scope captures seem to indicate the issue is not over-current, but under-voltage;  Both High and Low side FET drives turn off, and Soft Start goes through its hiccup mode cycle (7 soft-start charge-discharge cycles).  A closer look at the FET drive PWM at the time of the current transient shows only 3 or 4 PWM cycles before the hiccup (concurrent with rise in output current), which is not consistent with an over-current detection (7 accumulated overcurrent counts/32 PWM cycle).  Enclosed are a basic schematic (soft-start circuit for FETs not shown).  I've changed the compensation network values, and I changed the inductor current sense resistors to better match the inductor at higher temps, so those values as shown in the schematic are not correct.

    Thanks,

    John

  • 0 in reply to John Muren
    TI__Expert 4350 points

    John,

    The attachment did not come through, but it sounds like you figured it out so no need. Can you see the DIFFO pin dip enough during the transient to confirm that it drops by more than 16% (or as little as a drop of 13% per the performance table)?

    Regards,

    MC.

  • 0 in reply to Martin Cardella
    Prodigy 135 points

    Martin,

         I haven't been able to verify at the node yet, only at a output voltage test point far away from the regulator that shows a fast-going transient ringing on the output with a period of around 5.4ns with a peak-peak of 2.4V lasting for two or three cycles, concurrent with the FETs turning off, but again that was at a remote point.  I need to make some modifications to the board case to reach that node and make measurements. 


    Thanks,

    John

  • 0 in reply to John Muren
    Prodigy 135 points

    Martin,

         I verified that the DIFFO node is indeed dropping below the 4V point, more than enough to get an undervoltage.  The output itself doesn't look as bad as DIFFO.  I notice that on the datasheet, the schematic shows a 20Ω resistor between VOUT and the VOUT pin on the TPS40131;  I don't have this on my board.  I will add this, with perhaps a capacitor to form a low pass filter at the VOUT node.

    Thanks,

    John