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To much Output ripple PTH08T240W

Andreas Grüttner
Prodigy 100 points
Other Parts Discussed in Thread: PTH08T240W

I'm using a PTH08T240W on a 125MSPS ADC Board to power FPGA and other components.

Therefore I need preferably less ripple at power rails to get a clean FFT spectrum from ADC data.

Datasheet states a Vo ripple of typ. 10mVpp (20MHz BW).

Input of circuit is 12V and output 3.6V.

I have measured output ripple with scope BW limited to 20MHz and a probe with short GND tip.

Output ripple measured is around 40mVpp.

What in my schematic or pcb design can be wrong resulting in increased Output ripple?

Here my schematic and scopeshot from measurement.

best regards

Andreas

  • 0
    TI__Mastermind 38230 points

    Hi Andreas:

    I revewed the schematic and identified two possible reasons for this high ripple .

    First , The output polarized capacitors C81E and C81F ,T491D337M010AT, ESR 0.5 ohms cannot be used  with turbo trans resistor R81C, 28.7kΩ. The ESR  must be <15mΩ as required by Turbo trans function. T491 series cannot be used with turbo trans function.

    I recommend remove R81C in this application or replace these two capacitors with 330uf ESR <15mΩ.

    Second: ( after R81C removed) Add in additional ceramic capacitance 47uf to 100uf to reduce ripple . 

    Tom

  • 0 in reply to Tom Guerin
    Prodigy 100 points

    Hi Tom,

    many thanks for your help.

    I have tried something like recommended.

    First, replacement of C81E and C81F with T520X337M010ATE025 (ESR 25mR) has no effect.

    This capacitor type is recommended in datasheet but output ripple is unchanged 40mVpp.

    Second, then I removed R81C (TT-Resistor) and added in a 47uF ceramic capacitor at output.

    Now output ripple is 32mVpp.

    I think, component choice and schematic is now alright but I must looking for a layout problem.

    Can you help me?

    I would like send you screenshots from all layers in area of U81 and whose external components.

    Currently I redesign this board and have a chance it making right.

    best regards

    Andreas

  • 0 in reply to Andreas Grüttner
    TI__Mastermind 38230 points

    Hi Andreas:

    I revewed my data where  ripple was measured with close coupling directly across the 47uF ceramic capacitor. The wave form is sinosodial .

    The average ripple was about 21mV with a 6 Amp load.  I recommend to attentuate ripple by at least 30%-50% or more  , add additional ceramic capacitors ( 100uf x 2) or 47uF x3-4 The ripple data is

    Tom

  • 0 in reply to Tom Guerin
    Prodigy 100 points

    Hi Tom,

    23mVpp ripple is almost triple of value stated in datasheet diagram for 3.3V output voltage.

    Solution with more ceramic capacitance and without Turbo-Trans is good for the existing boards.

    For a redesign, I want a clean solution with output ripple of max. 10mV.

    Can I get it with a PTH08T240W?

    Do you have a pcb design or eval board where I can get helpful tips for a good layout?

    best regards

    Andreas

  • 0 in reply to Andreas Grüttner
    TI__Mastermind 38230 points

    Andreas:

    The pubished ripple is the typical ripple  for all power modules.

    Can you send me an E-mail for further discussion off line. I used a different module  , lower maximum voltage . the average ripple is14mV no 23mV. Sorry.

    tguerin@ti.com

    Thanks Tom