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DC/DC Controller (External Switch) Iout (Max)

Kazuhiko Ogawa
Intellectual 985 points

Could you please let me know?
How the Iout (Max) of the DC/DC Controllers were determined in “ Power Management Guide (slvt145m)“ 37-page and/or Parametric on each Device Description web page?
http://www.ti.com/lit/sg/slvt145m/slvt145m.pdf

I think Iout (Max) depends on I(drain) capability of the external power MOSFET.
Otherwise,
Was this Iout (Max) calculated from Gate driver current, fsw, MOSFET Gate charge Qg, …..?
What is there the Equation for Iout (Max)?

Best Regards,
Kazu Ogawa

  • 0
    TI__Intellectual 1435 points

    Ogawa-san,

    You are correct that maximum Iout is related to gate drive strength.    Footnote 2 reads,     

    "2  Current levels of this magnitude can be supported with commonly available commercial FETs."

    The maximum current is not calculated but based on applications experience.   Higher currents are possible with superior FETs or with gate drive enhancement such as bipolar emitter followers. 

    Best regards,

    David Pace

     

  • 0 in reply to David Pace
    Intellectual 985 points

    Thank you very much for your answer.

    I think,

    The relation between the Gate drive current Ig and the MOSFET is the following FET Switching loss (Psw).

    Psw= t x fsw x Vin x Iout ,       t= Qg/Ig

    The total MOSFET power loss is the following by summing up Psw and FET Conduction loss (Pcnd).

    PFET= Psw + Pcnd

    MOSFET level thermal design is required by FET thermal resistance (Theta-ja, Theta-jc) and PFET.

    Tj= Ta + (Theta-ja*PFET)

    It’s important to concern about the MOSFET level thermal design.

    Is above my thoughts is right?

    Would you please advise me?

    Best Regards,

    Kazu Ogawa

  • 0 in reply to Kazuhiko Ogawa
    TI__Intellectual 1435 points

    Hello Ogawa-san,

    I agree with your thoughts but have a problem with the first equation.  

     If the gate drive current is supplied from Vin because there is no external bias supply and bias current is not drawn from Vout,   then the losses due to gate drive are the average gate current times Vin.   The average gate current is fsw x Qg.   Therefore,

    Igate =  fsw x Qg  

    Pgate =  fsw x Qg x Vin.

    The switching loss in the buck MOSFET  is the loss in the FET during the rise time of the SW node.

    Psw  =   0.5 x Vin x Iout * tr / T

    The 0.5 x Vin  factor represents average voltage across the MOSFET during the rise time.   The rise time tr much less than Qg/Ig because the drain voltage swing occurs only during the plateau region of the gate voltage waveform.    The rise time is something like   Cgd x Vin / Ig,  where Cgd is the average gate-drain capacitance for Vgd = 0V to Vin.