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Transient response of LM26420

wayne Robson
Prodigy 50 points

I'm doing sustaining work on a board with a LM26420 DC/DC converter.  The transient response is poor with an approximate 0 - 1.2A step in load current.  How can I go about optimizing that?  I'm not finding any ap notes or spice models for this part.  I'm imagining adding a Type 3 compensation cap as per slva352a would be a good thing but would need to be adjusted slightly for this device/ topology.  Adding more capacitance couldn't hurt.  The current output cap is 33 uF.  Thanks for your feedback.

  • 0
    Prodigy 50 points

    BTW - The schematic is drawn as per Fig 45 in the data sheet.  Vin=5V, Vout=1.2V@ up to 2A.

  • 0 in reply to wayne Robson
    TI__Genius 16025 points

    Hi Wayne,

    Are you seeing load transient behavior that is significantly different from the datasheet? If so, please provide some waveforms of the transient so I have a handle on what the issue is.

    Thanks,

    Anston

  • 0 in reply to Anston Lobo
    Prodigy 50 points

    Hi Anston,

    I can't provide scope photos immediately but can describe the function in a little more detail.  Photos to follow if needed.  The 1.2V power rail is used to power FPGA IO.  The IO is configured as a 64 bit DDR data bus running at 300 MHz.  Edge rates are on the order of 1nS.  The IO is terminated to Vtt=0.6V through 50 ohm resistors.  The worst case power demand is when all outputs switch from '0' to '1'.  In this case the power rail must provide ~768mA ( 64*(1.2-0.6)/ 50 ohm) with a 1nS rise time.   

  • 0 in reply to wayne Robson
    TI__Genius 15810 points

    Hello Wayne,

    It definitely would be helpful to see some scope shots to be able to suggest a BOM change for a more optimized load transient response. As such, adding more output caps to a peak current mode architecture is not an issue, but you do limit your bandwidth of the system and this in turn makes the system sluggish to change. Adding a Cff capacitor in parallel with the upper feedback resistor is also helpful only to a certain degree. The Cff cap adds a pole and a zero to the overall loop and if not chosen properly, it could in fact de-stabilize the system.

    What I have experimented with is that the Cff capacitor value should be chosen such that the crossover frequency of the system without the addition of the Cff cap is a geometric mean of the zero and pole frequencies caused by the Cff capacitor. This means that you'd need to obtain a bode plot of the system without the Cff cap, record the value of the crossover frequency (fx) and then use it to calculate the value of the Cff cap according to the following equation:

    Cff = 1/(2*pi*fx)*1/sqrt(Rfbt*(Rfbt||Rfbb))

    You will see some improvement over your existing response, but I am not sure that you will see something dramatic. I hope this helps. Please let us know and if possible share your transient performance results before and after the addition of Cff too.

    Regards,
    Akshay

  • 0 in reply to Akshay Mehta
    Prodigy 50 points

    Hi Akshay and thanks for your feedback.  I apologize for the delayed response.  I'm in the middle of an office move.  After further review, I will add a few more details...

    Using better measurement techniques, the measured ripple associated with load transients is approximately 50 mV for a 1.2V output.  If possilble, I would like to improve that but realize we're approaching as good as it can be.

    I'm not sure how I can measure the bode plot for the system.  That would require an eval board or something that was instrumented properly and test sources etc to acquire meaningful data.  I was reviewing TI doc slva352a for more information regarding compensation.  Table 1 Type 2B compensation appears to describe the fp1 and fz2 you are requesting I measure.  It would be possible to calculate the fp1 and fz2 values based on internal compensation component values if they were known.  They don't appear to be detailed in the data sheet.  Would it possible to get these numbers for this device?  Thanks again.

    Wayne 

  • 0 in reply to wayne Robson
    TI__Genius 15810 points

    Hello Wayne,

    I also am not in possession of the internal compensation values. It would indeed be much easier to model the loop and calculate the value of Cff needed. Since I did not know that, I suggested the alternate two-step method.

    To measure the bode plot of the system, you'd need an EVM. They are available to purchase on the TI website. If you go through with the purchase, then on the board you will see traces going for each vout to resistors R1 and R2. These are the two upper feedback resistors for their respective Vouts. To measure the Bode plot, you'd have to interrupt this connection and insert a 100 ohm resistor from the Vout trace to the upper feedback resistor. You could use a leaded component. Once you have that, you could use a network analyzer to inject an AC signal and plot the systems response to the perturbation in the frequency domain. Here in our lab we use AP instruments frequency response analyzer. 

    If you are not sure of how to use it, you could send us your detailed schematic and and we could take a look at it and try and suggest BOM changes. This approach might take a little while. Also when you measured the ripple, did you mean 50mV of over/undershoot on Vout when the load transitions? I am tempted to say that it might be the boundary of the chip's performance. How fast are you transitioning the load and what levels are you toggling it between? 

    I hope the information helps.

    Regards,
    Akshay