TPS54232 heat design

The EVM for TPS54232 is built on a 2" x 2", 2 layer pcb.  The bottom layer is a dedicated ground plane with one smal signal etch.  The top layer is about 50% ground.  It is a conservative design to allow a low temperature rise to the IC junction.  In general, dc/dc converter ICs with integrated FETs use an exposed pad to transfer heat directly to an internal or bottom side ground plane that will usually be a full layer.  TPS54232 does not have an exposed thermal pad.  Te vias directly under the IC may help to transfer heat.  I do not have any calculations to determine required copper area.  I based that design on previous experience.  There is a plan to develop a PCB copper area calculator.  I do not know the time frame for it though.  Probably not soon enough to help with any current projects.