Good morning TI E2E,
In the TPS51200 datasheet, Pg 17, Layout Considerations, Bullet 7 states in part:
“The GND and PGND pins should be connected to the thermal land underneath the die pad…”
Also on Pg 17, Bullet 6 States:
“The negative node of the VO output capacitors and the REFOUT capacitor should be tied together by avoiding common impedance to the high current path of the VO source/sink current”
Does bullet 7 really mean run traces under the package from both Pin 4 (PGND) and Pin 8 (GND) to the thermal land under the package, or does it simply mean just make sure that both of these pins are electrically connected together?
The reason I ask is because if bullet 7 really means run traces under the package from both pins 4 and 8 to the thermal land under the package that would seem to violate Bullet 6 “…avoiding common impedance to the high current path of the VO source/sink current” ?
In addition the TPS51200 evaluation board layout only has a trace under the package to the thermal land from pin 8, and not pin 4. Pin 4 is routed outside the package to vias into the ground planes. Furthermore, the Top Side Copper on the evaluation board has the ground plane “channeled” under the package. Suspect this is to keep noisy VO return currents flowing back through the PGND pin rather than back through the GND pin and generating noise on the REFOUT pin. All of this points to DON’T run a trace under the package from Pin 4 to the thermal pad, only do that for Pin 8, but given the language in Bullet 7 of the datasheet need to make sure.
Thanks,
-John
