Hi,
Our customer has asking us to show TPS53014 recommended pattern layout.
Would you please let me know the layout guide line document.
Thanks and regards,
T.Imi
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi,
Our customer has asking us to show TPS53014 recommended pattern layout.
Would you please let me know the layout guide line document.
Thanks and regards,
T.Imi
The layout guidelines are in the datasheet:
• Keep the input switching current loop as small as possible.
LAYOUT SUGGESTIONS
Place the input capacitor close to the top switching FET. The output current loop should also be kept as small as possible.
Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedback pin (VFB) of the device.
Keep analog and non-switching components away from switching components.
Make a single point connection from the signal ground to power ground.
Do not allow switching current to flow under the device.
You can also look at the EVM users guide. There are pictures of the layers on pages 14, 15 and 16:
http://www.ti.com/lit/ug/sluu943/sluu943.pdf