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LM3480 Failing at 24 VDC input

Michael Piklula
Prodigy 20 points
Other Parts Discussed in Thread: LM3480

I am having a large percentage of failures of this regulator testing the units with no load.  Output capacitor is 10 uF, input is 4.7 uF in parallel with 0.1 uF.  Supply is 24 VDC.  Board is a mature product for over 8 years, never had this kind of issue.  Testing a sample lot of 50 pieces with a 20 volt input resulted in 0 failures, moving that up to 24 volts and retesting the same pieces resulted in 17 failures.  Output voltage typically goes to supply levels when it fails.  So devices appear to be sensitive to higher input voltages, even though spec says they can tolerate 30 volts.  I had some old National Semiconductor parts in lab to replace the blown ones with, they all worked just fine.  So what has changed in the last year?  We have tried a second lot of parts and this later lot was even worse on failure rates.  It appears something has changed in the manufacture of this device.  I tried a Richtek cross and had 25 of 25 pass with no failures.

  • 0
    TI__Prodigy 60 points

    Hi Michael,

    My name is Andy Lutz and I am a Customer Quality Engineer at Texas Instruments supporting the LM3480.    Thank you very much for alerting us about the behavior you are observering.    So we may investigate further, I would appreciate you kindly contacting me at the Email Address below.

    Best Regards,
    Andy Lutz
    andy.lutz@ti.com

     

     

     

  • 0
    Prodigy 50 points

    Hello Michael,

    I to have just experienced the very similar drop-out rate (20%) on the LM3480. All of my design criteria are also the same as yours; in my mind I found the Holly-Grail, your data saved me lots of time. This LDO is only used only for biasing and simple analog circuit and if the LDO fails it fails right out-of-the-gate.

    I do realize this post is like 2+ years old but I am wondering if you ever got any resolution from TI?

    You may reply to my email below.

    Steve

    slane@extratech.com

  • 0 in reply to Steve Lane5
    TI__Expert 8905 points
    Hi Steve,


    Could you provide scope captures showing start-up and shut-down? I was not able to dig up what happened on the older post, but I can help for your current problem.

    My first guess is an over-voltage or reverse current event, which would cause EOS damage on the device.

    -David
  • 0 in reply to David Hopkins
    Prodigy 50 points
    Hi David,
    Thanks for your response.

    I can't get ya a scope capture quite yet but I have attached a screen-shot of the schematic showing the LM3480 and the analog circuit that requires the +12V biasing. In short, the Vin (+24V) comes in from the outside world and Vout (+12V) is ONLY used for the Q1/Q2 biasing circuit. This design has two supplies, +5V (logic) and +12V (bias). Turns out, on this system, the +5V is present before the +24V comes up, so for ~30 seconds there is a reverse current/voltage event that originates (back-feeds ~+4.5V) from Q2 onto the +12V rail/Vout pin of the LDO.

    For now I will add a schottky across the LDO (Vin/Vout) for some protection because I cannot do anything about power sequencing; if I turn the PCB I will replace the LDO w/a RC protected one.

    ...rats, I just noticed there is no button to click and attach a document, so if you want to provide me an email, I can send you the schematic circuit I was referencing above. Am I missing something?

    Respectfully,
    Steve
    slane@extratech.com
  • 0 in reply to Steve Lane5
    TI__Expert 8905 points

    Hi Steve,

    Easiest way is to typically just take a screen-shot of your schematic and post it. Information on how to post it below:

    -David

  • 0 in reply to David Hopkins
    Prodigy 50 points

    Hi David,

    Attached is a screen-shot of the circuit I mentioned in my last post regarding the LM3480 failures. Note that I installed a 100V/1A schottky diode across Vin and Vout in case RC was the issue.

    Even though there could be a condition of reverse current I isolated (dis-allowed the +5V to turn-on) the +5V and only turned-on the +24V to this LDO with like a 10mA load and the LDO still failed. I then tested other PCBs and this time started with +20V with no failures. I then stepped up the voltage and I experienced failures between +24V - +26V.

    I now believe that reverse-current is not failing this LDO but EOS on the input as low as +24V.

  • 0 in reply to Steve Lane5
    TI__Expert 8905 points

    Hi Steve,

    Have you checked Vin to see if you have any over-voltage spikes on it during normal operation? You have very little input capacitance, especially once you factor in the voltage derating. You could have spikes in voltages due to other conditions on the 24V rail that cause it to exceed the operating conditions.

    -David

  • 0 in reply to David Hopkins
    Prodigy 50 points

    David,

    The +24V rail is dedicated (nothing else is on this +24V rail) to this Vin (U3) for the LDO plus there (not shown) is a 1.0uF cap (C2) prox to the input header where the +24V comes onto the PCB. As soon as I get time I plan to take a look (w/a scope) at the +24V as it comes up. I have attached a screen-shot of the layout, quite simple stuff here and is per the data sheet. Maybe I should bump-up the Cin and Cout to 0.47uF?

    Steve

    Thanks for the response.

    Steve

  • 0 in reply to Steve Lane5
    Prodigy 50 points

    Typo...C2 (1.0uF on the +24V input to PCB) is not shown on the schematic screen-shot but is shown on the layout screen-shot...
    Steve

  • 0 in reply to Steve Lane5
    TI__Expert 8905 points
    Hi Steve,

    Yea I would try increasing the cap - especially for off-board power.

    -David