• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 63 subscribers
  • Views 326 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

cascading tlc5971s

mahmut turk
Intellectual 300 points
Other Parts Discussed in Thread: TLC5971

Hello all,

I have a question about cascading tlc5971s. What is the maximum number of tlc5971s that can be cascaded in series? i couldnt find the answer at datasheet. 

Thank you.

  • 0
    TI__Intellectual 1820 points

    Hello Mahmut,

    5971 maximum cascading number is decided by frame rate.
    5971 support max 20MHz data transfer rate, the shifter register length is 224bit. If you need 60Hz frame rate, then the maximum cascading IC number is 20MHz/224/60=1488pcs.
    If you need 30Hz frame rate, then this number can be doubled.

    Best regards

    Mike

  • 0 in reply to Mike(DC/DC) Wang
    Intellectual 300 points

    Thank you Mike. This is what i expected to hear.

    I also wonder why the ic is drived differently(external clock is used as pwm clock) when it is used in video applications. at page 28 of data sheet, it is said :

    "This mode is ideal for video image applications that change the display image with high frequencies or for certain display applications that must synchronize all TLC5971s"

    i always assumed that although internal gs reference clock is used, all ics are still synced since all of them lacth the buffered 224 bit when they all wait more than 8 clock. so they become synched.

    and i am aware of that  the internal clocks of individual ics are not synched. but will this effect the video quality?

    in my application i drive the led display (with tlc5971) at 60 fps. and i am planning to use internal gs clock. will it affect the quality of the video?

    thanks,

  • 0 in reply to mahmut turk
    TI__Intellectual 1820 points

    Hi Mahmut,

    Internal GSCLK frequency have variation from 6MHz to 12MHz.
    In your case, frame rate is 60Hz. For one IC, for example, with ~7.86MHz internal GSCLK, 2 display periods are included in one frame period; While for another IC with 8MHz internal GSCLK, it may finish 2 display periods plus a small fraction of the 3rd display period in one frame period. When GS is low, e.g, GS=1, then the 1st IC may have 2 GSCLK period on time, and the 2nd IC may have 3 GSCLK period on time in one frame period. The brightness may have little difference between these two ICs(the brightness of 2nd IC is 1.5 times of that of 1st IC).
    If frame rate is lower, say 25Hz, then there will be more display periods included in one frame period. The brightness difference caused by 1 GSCLK period will be less noticable.

    This difference only can be possibly observed(different people have different feeling) in low grayscale condition(such as,GS <3). When grayscale data become larger, there will be many segments in one display period having some GSCLK on-time, then basically you can't feel any difference.

    No matter internal GCLK mode, or external GCLK mode, the schematic have no difference. You can go with internal GCLK mode, I think. After finished, you can check with some image pattern, then decide if it's needed to change to external mode. Only the software in FPGA need be reprogramed.

    Best regards

    Mike

  • 0 in reply to Mike(DC/DC) Wang
    Intellectual 300 points

    Hello Mike,

    ı havent focused to the point about internal oscillator's frequency so far. in datasheet it is written as what you said exactly (6 to 12 mhz). it is typical value is 10mhz however. i wish all ics operate at typical oscillator frequency or i may need to change my design :)

    i'll take your suggestion into consideration. 

    thank you very much Mike,