Gate Driver application circuit

Hello. I am using an NMOS transistor as a simple analog switch between a supply and load. The supply is +28V, the load is a RF GaN Power Amp. As a test scenario instead of using the GaN PA I used a 6 ohm resistor to mimic the amount of current the +28V would see when the PA was saturated. My application circuit shows that during turn on the pulse looks clean and responds fairly quickly and rises fairly quickly as well. However, on the falling edge there is a very slow fall time, on the order of 30usec. The NMOS gate is being driven by an LM7171B op amp that is configured as a non-inverting amplifier taking a 0 to +5V input and providing 0 to +33V to the NMOS transistor gate. The NMOS transistor is SI7322DN from Vishay. I was curious as to the reason for the slow turn off. Any suggestions to improve the fall time of this circuit?