TPS56221 will not start up under load

The EVM documentation implies the EVM will start up under no load and full load conditions.  Perhaps your input supply is current limited.  Are you using an electronic load?  If so, you may need to set it to constant resistance rather than constant current mode.  Otherwise can you post some waveforms that show your start up (or lack of) behavior?

I am using an electronic load. I will try the constant resistance setting. I will post wave forms of the behavior.

Ken

Ken,

Can you post your schematic and some waveforms? Please monitor Vin, EN, Vout, and either inductor current or load current (inductor current is preferable).

Also let me know what your system requirements are:

- Vin range, Vout, Iout, and load transient specs if any.

Regards,

MC.

Attached are two waveforms. One shows power-up under a 0.5 amp load and the other at 1 amp load. Under 0.5 amp load the regulator comes up after the hiccup cycles. Under 1 amp load regulator stuck in overcurrent mode.

I tried constant resistance on the electronic load and the regulator will come up with a 0.1 ohm resistance (1V @ 10A)

0.5A load.

1A load. Stuck in over current.

-Ken

MC,

In my application I am using 12V input (10.8V-13.2), 3.3V +/-5% output at 25A.  A schematic for the 3.3V I/O supply is attached.8233.schm0055-001_3v3_io.pdf

-Ken

Ken,

I don't see anything obvious in your schematic other than R756 from pin 1 COMP to ground. It says DNL and 0-ohms. Is it depopulated? Is your desired Fsw 500kHz?

Once the switcher is up and regulating, how much load will it support?

Can you post a pic of SW node at the highest load the switcher will support? If possible, include the ILIM pin waveform on the same pic. ILIM is the LFET gate drive after the calibration is done. Timebase should be such that a few switching cycles are captured.

MC.

MC,

R756 is not populated to set Fsw to 500kHz. Once switcher is up and regulating it will support 25A.

I will provide the waveforms you asked for.

Thanks,

Ken

MC,

Here is a waveform capture of the SW node (purple) and the ILIM pin (yellow) under 25A load.

Thanks,

Ken

Ken,

That waveform looks ok other than showing a lot of switching spikes. You may want to investigate the power layout and placement of the snubber.

Since the switcher supports full load once up, then have a look at the inductor current during soft start. You may be able to detect current levels that would be expected to trip OCP. Your schematic shows 500uF of output cap. Is there more elsewhere in the design that isn't shown? The surge from charging those caps with the given SS cap of 82nF only accounts for 335mA and can't directly explain OCP. Also note, some e-load have a startup profile that can significantly exceed the load setting.

Regards,

MC.

MC,

There are 10uF caps near each of the 12 sockets for the add-in cards. I can't get the regulator to start up even at 0.5A load.  if I remove the ILIM resistor it will start under all load conditions. Can you give me advice on how to look at the inductor start-up current?

Thanks,

Ken

Ken,

An extra 120uF still can't explain the OCP. And removing the ILIM resistor disables the OCP altogether, so proceed with caution.

Ideally you would need to use a current probe. The one I have on my bench is a Tek TCPA300 which works fine for this. If you have access to a similar probe, you would need to lift one end of the choke and insert a wire loop just big enough to accommodate the clamp-on current probe. The added wire loop needs to be sufficient gauge to support your 25A load.

Find attached an example of the probe setup.

If you don't have access to a current probe, then it gets more difficult. A shunt will work, but it will not yield much voltage signal. Typically shunts only provide 10's of millivolts, so a scope measuring this voltage will have a poor SNR, and it is a floating measurement. If you do end up using a shunt, place it in series with the choke, on the DC side. It would be nice to be able to use a larger value shunt that yields a larger signal, but that isn't an option because it will change the results.

A less invasive option would be to place an R-C filter directly across the choke (R to the AC side of the choke, C to the DC side). If you match the time constant of this RC with the time constant of the choke and its DCR (so make RC = L/DCR, and start with an R value of about 1k and calculate the required C), then the voltage across the C will be a replica of the voltage across the DCR (only if the time constants match). A choke like this will have a DCR in the range of a few milli-ohms, so the voltage across it is also very small and won't be better SNR than a shunt would give, and is also a floating measurement.

Ex: with a DCR of 0.001 ohms with 25A will only drop 25mV. So if you match the two time constants, the voltage across your added C will only be 25mV. If the time constants are not matched, the DC drop across your C will still be correct, but the AC ripple across it will not match and will definitely confuse the issue. This RC method is a long shot and in this case use it as a last resort. The best is a current probe as pictured.

If you have the probe, the capture the full startup event. If you see excessive current, you can recapture with finer detail and hone in on the peaks of the inductor current. You need to verify if these peaks are exceeding the expected OCP level. In your case, the expected OCP is 29.9A of DC load, or 26.2A at the valley of the inductor current.

Regards,

MC.

MC,

We have a current probe but it is being used in another lab right now. When it becomes available I will make the measurement and send you the waveform.

Thanks,

Ken

Hi MC,

I was able to make the measurement with the current probe. the attached waveform shows a pretty nasty current surge at turn on. This is probably the culprit. This is with no load so I am wondering what can be causing such a harsh spike?

Thanks,

Ken

Ken,

Where are you measuring the current, and what's the scale?

I can see it says 20A/div, but I'm hoping there's a scale factor that isn't mentioned.

Regards,

MC.

MC,

Current probe is on the load side of the inductor. Current probe is a 10:1.

-Ken

MC,

I have attached two scope shot. This time I put a probe on the SS/EN pin. You can see that the SS pins starts its calibration pulse the right at the falling edge of the second "sawtooth" you can see the large current spike. Its kind of faint but it is there if I adjust the sweep out further.

Thanks,

Ken

Ken,

For the two most recent scope shots, it looks like the scale is 5A/box as shown, is that correct? I calculate an expected choke current ripple of about 7.4A p-p, which coincides with the thick hash part of the 1st current trace.

If that is correct, then the current spike is in excess of 35A and would be expected to trip your OCP. We've seen some e-loads with a severe startup overshoot, although not quite this high. I am discounting the possibility that your choke is saturating since it does operate and support full load once up. You can verify for sure that the current glitch is from the load by moving the current probe to the load wires instead of the choke. If you see it there, then you have the answer.

Another thing you can do is to temporarily set up with a real resistor load, preferably representing full load of 25A. If then the switcher starts up as desired, then that would confirm the e-load interaction.

Regards,

MC.

MC,

I want to clarify that these scope shots were taken from our board under no load. I did not have the electronic load connected.

Ken

I will try to connect to the electronic load but set it for constant resistance mode and see if the hiccup startup condition still occurs.

Ken

Ken,

Sorry, my misunderstanding. So we still need to figure out where the surge current is coming from. Can you confirm that your SS cap is the value you expect? It looks like it is supposed to be 82nF. I just noticed that the SS line goes offpage. Where does it go and is it possible that the external connection is pulling this pin up more quickly than expected? If so, then the SS surge will also be higher than expected.

Can you take another snapshot of EN/SS during the first startup similar to the one you posted on Apr 09 2014 17:49 PM, but at 2mSec and 1V/box? And also when the device is in hiccup?

If the surge is observed with no e-load connected, it won't be better when connected. The surge must be unrelated to the e-load. Also, from your previous pics it looks like the surge occurs only during the first startup attempt but not afterwards. In the next pics you take, can you add Vout and Vin simultaneous on the pic?

Regards,

MC.

MC,

The SS/EN pin goes to a CPLD which turns on the TPS56221. I had adjusted the SS cap to be 0.1uF to increase soft start time to see if that was the issue. That is why the SS signal ramp up is slower than expected if using a 82nF cap.

I will get the scope shot you asked for soon.

Thanks,

Ken

MC,

Here is a waveform shot with SS pin (yellow), Vout-3.3V (green) and Inductor current (blue) with scope set for 1V/div and 2ms timescale.

Thanks,

Ken

Here' s one with where we can see the hiccup mode.

Ken,

Now we can see where the current surge is coming from. The output voltage has a step change at the first few pulses from SW, right where the current surge is, and where it first goes into hiccup. The output should be soft-starting with a ramp, not a step. That step implies a huge current surge, and is the reason behind needing soft start. The second stair-step in the output has a more controlled dv/dt to it, and it doesn't start from zero, both of which help reduce the current surge. That's why the second attempt avoids OCP.

Please change the timebase to 5 or 10uSec/box and trigger on that first edge (either the current or Vout), and look at the SW node to GND. That should pinpoint the anomaly.

Also note, the SS ramp should be quite linear all the way up to about 5.5V where it levels off. Your SS has some non-linearity to it, indicating that your CPLD is affecting the ramp (or the 56221 device has some damage). This may not be a problem, and may not be related to the issue at hand, but keep it in mind. Whatever you have hooked to EN/SS should be open collector, active pull down only.

Regards,

MC.

MC,

Here is the waveform capture with SW node (yellow), Vout (green) and inductor current (blue) @ 5uS/div

Thanks,

Ken

Ken,

The extra wide pulses are indeed the source of the current surge. There are a few things that can cause unexpected pulse width like that. Like any voltage mode switcher, the pulse width is determined by the comparison of the PWM ramp and the COMP voltage. The PWM ramp is internal, and is likely not the problem.

I see you have pulled the FB pin off page, node "VDD_3P3V_IO_TRIM". The FB pin and the COMP pin are related through the gain of the error amp, so if there is something happening on FB from an external source that is coincident with the surge, that may be the problem. Have a look at that off page connection, or you can simply disconnect the external connection to see if the current surge is no longer there during soft start.

Another possibility is that ambient noise affect this operation, and in the case of the 56221, noise issues would most likely be due to noise on the BP pin 19. The BP is the regulated supply for most of the device, and it also powers the gate drives. Gate pulse current can impress transients on BP if the layout / connection of the BP cap is not done well. Ideally the BP cap should be placed right up against the BP pin and GND PowerPad, with minimal trace length, and these traces should not be routed through the power traces. The power traces are: input cap + to VIN pins, input cap - to PowerPad, SW node to choke AC pin, choke DC pin to output cap bank, cap bank back to PowerPad. All of the low power analog circuitry, including BP, should not be in the power path described above.

The 56221 (and 56121) incorporates internal NexFETs. These FETs switch extremely rapidly and result in both extreme dv/dt at the SW node, and extreme di/dt in the Vin caps. For this reason, the input caps need to be as close to the device as your manufacturing rules allow. Similarly, the SW copper area should be minimized, and the choke AC pin should also be as close to the device as your manufacturing rules allow, and the SW node copper should only be big enough to cover the associated pins. The SW node is not the right place to add heat sinking copper area, as the parasitic capacitance from the additional copper plane can result in a lot of ringing. The DC pin of the choke and the output cap bank should loop back toward the PowerPad, not out toward the load. This will minimize the impedance of the output filter and minimize the generation of output ripple at the source. You can then route the DC output current as needed, and will likely need additional local decoupling caps at your load. All of the noise mitigation techniques described above hold true for any switcher like this and are not specific to the 56221.

If you would like a sketch of the layout suggestions above let me know. Also let me know what you find at the FB pin.

Regards,

MC.