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Hi folks,
The following is my layout for TLV61225 / TPS61221. I would like to borrow your eyes to have a look at the layout and see if it confers any EMI problem.
The reason I ask is, I don't quite understand the suggested layout in datasheet (Page 15). EN & Vin, Vout & FB pins are connected through vias and traces on another layer. I think both of those pairs of pins can be connected through traces on top layer without any vias which I did in my layout.
My layout seems work fine but I don't want risk a EMC test failure.
My layout: I installed an extra resistor (R1) for current measure.
Suggested layout:
