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TPS65910A / DEV_OFF and DEV_OFF_RST

Ryuji
Guru 20090 points
Other Parts Discussed in Thread: TPS65910A
Hello,
 
Please let me know the behavior about DEV_OFF and DEV_OFF_RST of TPS65910A.
We boot TPS65910A by BOOTMODE 10 and PWRHOLD is tied High.
Then we write VDD1_OP_REG to 0x2C(EEPROM default is 0x2B).
 
<Question 1 : DEV_OFF>
If we set DEV_OFF bit to "1",  TPS65910A will be power down and reboot after power down finished due to DEV_OFF bit is cleared and PWRHOLD is tied High.
After reboot , VDD1_OP_REG is kept 0x2C and other registers are keeping BOOTMODE 10 setting.
 
Is my understanding correct ?
 
<Question 2 : DEV_OFF_RST>
If we set DEV_OFF_RST bit to "1",  TPS65910A will be powered down and reboot after power down due to DEV_OFF_RST bit is cleared and  PWRHOLD is still tied High.
After reboot , VDD1_OP_REG is reset to 0x2B and other registers are keeping BOOTMODE 10 configuration.
In my understanding, TPS65910A register value will be reset to BOOT MODE10 default value when we set DEV_OFF_RST to "1".
 
Is my understanding correct ?
 
Best Regards,
Ryuji Asaka