• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 63 subscribers
  • Views 540 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS75003: heatsinking with LDO disabled

Philip Pemberton
Intellectual 255 points
Other Parts Discussed in Thread: TPS75003

Hi,

I'm thinking about using the TI TPS75003 to provide the core and I/O voltages for an Altera Cyclone II FPGA (2C5 type) and a PIC microcontroller (PIC18F85J50). Essentially, I'm looking at a modified implementation of the "SLVR282" reference design on the TI website: I don't intend to use the LDO (in fact, I was planning to wire the LDO's Vin to GND).

There is, however, a catch. The TPS75003 has an exposed thermal pad on the base of the IC. At the moment, my usual PCB fab company is closed due to Chinese New Year (and they don't reopen until mid-February), and my in-house PCB lab doesn't include a through-plating line. What this means is that I'm not going to be able to put vias under the chip, but on the flipside, the LDO (which according to the datasheet is the primary contributor to the thermal dissipation of the '75003) isn't going to be in use, so the dissipation should in theory be much lower.

 

Now onto the questions...

- What level of heatsinking is required for a TPS75003 which is being operated with the LDO regulator disabled? That is, how much heat needs to be dissipated?

- Is the disabling of the LDO regulator likely to cause problems with other parts of the chip? That is, can I float IN3, FB3 and OUT3, and then have the rest of the chip work as normal?


Thanks,

Phil.

  • 0
    TI__Expert 8890 points

    The only significant thermal generator in the TPS75003 is the LDO.  And the primary reason for the thermally exposed ground pad is to dissipated heat from the LDO.  Therefore you have nothing to worry about thermally by not connecting the exposed pad and therefore you require no additional heat sinking.  Page 20 of the data sheet says, "The two buck converters do not contribute a significant amount of dissipated power."

    But just to reassure myself I did some "back of the napkin calculations':  I looked at several 20-lead plastic packages (without exposed thermal pads) to find that the worst theta_ja that I could find was approximately 100degC/W.  For a max junction temp of 150degCand max ambient temp of 85degC such a package can dissipate around 650mW (Pdisp_max = (Tj - Ta) / theta_ja).  Your application will dissipate nowhere near this amount of maximum power in the part.  The quiescent current is only 150uA (max) which only amounts to 5Vcc x 150uA = 0.75mW. The average drive current to turn on/off the fets (both of them together) will not exceed 4 x 20nC x 400kHz = 32ma.  And if this current were dropped entirely across the part (which it is not) the power dissipation  would only amount to 32mA x 5Vcc = 160mW. 

    The consensus here is that you should not float IN3 or EN3 but ground them both.

  • 0 in reply to Bill Stokes
    Intellectual 255 points

    That sounds great, and answers my main questions -- thanks. I appreciate the inclusion of the "maths behind the answer", too. Now I can start putting together some prototypes!

    Just one last thing - am i right in thinking that I should connect FB3 to OUT3, or should I be grounding it?

    My gut feeling is that I should be wiring FB3 to OUT3, which would (per equation 16) give 0.507V out, but seeing as there's no input to the LDO it should just act as a "keeper" to stop the feedback input floating about, picking up noise and potentially causing the chip to latch up.

    Thanks again,

    Phil.

  • 0 in reply to Philip Pemberton
    TI__Expert 8890 points

    I like your reasoning. I don't like to have anything floating in my own designs.  Pulling these pins to ground might be another solution but may increase the quiescent current to ground.  Yes, barring the fact that it probably doesn't matter, your solution seems the most conservative.