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bq33100 two cells

Alexander Shutko
Prodigy 170 points
Other Parts Discussed in Thread: BQ33100

Hi. I have read docs (bq33100 datasheet, bq33100 EVM guide) and just can't figure out how to connect two cells instead of 5. Here is the schematic of my solar power module (solar cell 200ma_5.1v, supercapacitors 500Fx2.7v). Should I remove T4, T6, T7 and T8 with resistors ?

  • 0
    Prodigy 170 points

    There are two questions:

    1. What elements are redundant in this schematic? (I just copied schematic from EVM guide using supercap series connection table). It looks like I should connect VC5BAL to the ground (and remove T4, R25, R27, R28, C14), connect VC1, VC2, VC3 together (and remove R23, R24, T7, T8, C17, C18, R31, R32).

    2. Is thermistor (bq33100 TS input) is mandatory ? (Can I remove it and use internal one ? Should I connect TS to VCCPACK net or GND ?)

     

  • 0 in reply to Alexander Shutko
    Prodigy 170 points

    Ok. I'll ask another way - I created a schematic using datasheet as example to simplify things.

    1. TS pin is grounded because of plans to use internal thermistor.

    2. All redundant (i think so) elements are removed (for two 500F 2.7v supercapacitors).

    Could anybody say if this schematic correct ?

     

  • 0 in reply to Alexander Shutko
    TI__Guru* 76230 points

    Hi Alex,

    If the external thermistor is not going to be used, you should connect a 10k resistor to ground. Remember to make the appropriate changes to data flash to support the usage of the internal temperature sensor.

    also you will need a learning load circuit as we have in the reference schematic to enable capacitance and ESR learning to take place. Also your system voltage ought to be connected to VCC as the device is powered from that pin. you will need the charge fet to control the charging of the gauge as well as for capacitance learning. you need the RBI caps as shown in the reference schematic as that cap serves as backup power in the event of a brown out for the processor. your data and clock lines circuit is also needed to be able to communicate with the device.

     

    thanks

    Onyx

  • 0 in reply to Onyx Ahiakwo
    Prodigy 170 points

    Thanks for answer!

    As I can understand from your answer the balancing part of the second schematic is OK (i was not sure about VC1-VC5, VC5BAL and their FETs) and this (second) schematic needs charging FET, rbi capacitors, vcc connection, TS 10K resistor & lerning load circuit (as in first schematic). Am I right ?

  • 0 in reply to Alexander Shutko
    TI__Guru* 76230 points

    yes the balancing part is ok. And yes the second schematic needs all components as with the first. make sure to compare against the reference schematic in the  data sheet.

    thanks
    Onyx