HI,
In our design we are using TPS54326 DC-DC. The Powe Good Output is open drain and goes LOW when the Power does not reach its required value, theoretically...
In Board, the behaviour shows that if the Power is not Enabled the signal is Open Drain, with Power Enable going HIGH it goes LOW until Output reaches the required value?
1. How can I make the PowerGood Signal be LOW when Power Enable is LOW?
2. Why does the signal is HIGH though the Output is 0V.
Thank you,
Iris
